m88915t.vhd

来自「Vhdl cod for a clock for sp3e」· VHDL 代码 · 共 416 行 · 第 1/2 页

            OutSignalName   => "LOCK",
            OutTemp         => vlck,
            GlitchData      => lock_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => FBK_nwv'LAST_EVENT,
                      PathDelay         => tpd_SYNC0_Q0,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS ADJ;

    ----------------------------------------------------------------------------
    -- PLL Process
    ----------------------------------------------------------------------------
    PLL : PROCESS (pll_out)

        -- Timing Check Variables
        VARIABLE Pviol_SYNC     : X01 := '0';
        VARIABLE PD_SYNC        : VitalPeriodDataType := VitalPeriodDataInit;

    BEGIN
        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalPeriodPulseCheck (
                TestSignal      => pll_out,
                TestSignalName  => "PLL",
                Period          => tperiod_SYNC0_posedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & "/m88915t",
                PeriodData      => PD_SYNC,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_SYNC
            );

            Violation <= Pviol_SYNC;

        END IF;

        pll_out <= TRANSPORT not pll_out AFTER pll_delay + half_per;

    END PROCESS PLL;

    ----------------------------------------------------------------------------
    -- DIV2 Process
    ----------------------------------------------------------------------------
    DIV2 : PROCESS (mux_out, FREQSEL_nwv, rst_int)

        -- Functionality Results Variables
        VARIABLE PrevData       : std_logic_vector(0 to 2);
        VARIABLE CLK_div_2      : std_ulogic := '0';

    BEGIN
            VitalStateTable (
                StateTable      => TFFR_tab,
                DataIn          => (Violation, mux_out, rst_int),
                Result          => CLK_div_2,
                PreviousDataIn  => PrevData
            );

        IF FREQSEL_nwv = '0' THEN
            div_out <= CLK_div_2;
        ELSE
            div_out <= mux_out;
        END IF;

    END PROCESS DIV2;

    ----------------------------------------------------------------------------
    -- OUTP Process
    ----------------------------------------------------------------------------
    OUTP : PROCESS (div_out, OE_ipd)

        -- Functionality Results Variables
        VARIABLE Q0_zd              : std_ulogic;
        VARIABLE Q0_int             : std_ulogic;
        VARIABLE QX2_zd             : std_ulogic;
        VARIABLE QX2_int            : std_ulogic;
        VARIABLE QDIV2_zd           : std_ulogic;
        VARIABLE QDIV2_int          : std_ulogic;
        VARIABLE Q5Neg_zd           : std_ulogic;
        VARIABLE Q5Neg_int          : std_ulogic;
        VARIABLE D0_zd              : std_ulogic;
        VARIABLE D1_zd              : std_ulogic;
        VARIABLE Dxnor              : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE Q0_GlitchData      : VitalGlitchDataType;
        VARIABLE QX2_GlitchData     : VitalGlitchDataType;
        VARIABLE QDIV2_GlitchData   : VitalGlitchDataType;
        VARIABLE Q5Neg_GlitchData   : VitalGlitchDataType;

        VARIABLE Violation0     : X01 := '0';
        VARIABLE PrevData1      : std_logic_vector(0 to 3);
        VARIABLE PrevData2      : std_logic_vector(0 to 3);
        VARIABLE PrevData3      : std_logic_vector(0 to 3);

    BEGIN
            VitalStateTable (
                StateTable      => DFFRN_tab,
                DataIn          => (Violation0, div_out, D0_zd, OE_ipd),
                Result          => Q0_int,
                PreviousDataIn  => PrevData1
            );

            VitalStateTable (
                StateTable      => DFFRN_tab,
                DataIn          => (Violation0, div_out, Q0_zd, OE_ipd),
                Result          => Q5Neg_int,
                PreviousDataIn  => PrevData2
            );

            VitalStateTable (
                StateTable      => DFFRN_tab,
                DataIn          => (Violation0, div_out, Dxnor, OE_ipd),
                Result          => QDIV2_int,
                PreviousDataIn  => PrevData3
            );

        QX2_int := VitalAND2 (a => div_out, b => OE_ipd);
        QX2_zd := VitalBUFIF1 (data => QX2_int, enable => OE_ipd);
        Q0_zd := VitalBUFIF1 (data => Q0_int, enable => OE_ipd);
        QDIV2_zd := VitalBUFIF1 (data => QDIV2_int, enable => OE_ipd);
        Q5Neg_zd := VitalBUFIF1 (data => Q5Neg_int, enable => OE_ipd);
        Dxnor := VitalXNOR2 (a => Q0_zd, b => QDIV2_zd);
        D0_zd := VitalINV (data => Q0_zd);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       => QX2,
            OutSignalName   => "QX2",
            OutTemp         => QX2_zd,
            GlitchData      => QX2_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => div_out'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_SYNC0_Q0),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OE_ipd'LAST_EVENT,
                      PathDelay         => tpd_OE_Q0,
                      PathCondition     => TRUE)
            )
        );

        VitalPathDelay01Z (
            OutSignal       => Q,
            OutSignalName   => "Q",
            OutTemp         => Q0_zd,
            GlitchData      => Q0_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => div_out'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_SYNC0_Q0),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OE_ipd'LAST_EVENT,
                      PathDelay         => tpd_OE_Q0,
                      PathCondition     => TRUE)
            )
        );

        VitalPathDelay01Z (
            OutSignal       => Q5Neg,
            OutSignalName   => "Q5Neg",
            OutTemp         => Q5Neg_zd,
            GlitchData      => Q5Neg_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => div_out'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_SYNC0_Q0),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OE_ipd'LAST_EVENT,
                      PathDelay         => tpd_OE_Q0,
                      PathCondition     => TRUE)
            )
        );

        VitalPathDelay01Z (
            OutSignal       => QDIV2,
            OutSignalName   => "QDIV2",
            OutTemp         => QDIV2_zd,
            GlitchData      => QDIV2_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => div_out'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_SYNC0_Q0),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OE_ipd'LAST_EVENT,
                      PathDelay         => tpd_OE_Q0,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS OUTP;

END vhdl_behavioral;