cy2318anz.vhd

Vhdl cod for a clock for sp3e

                     PathCondition     => (Byte1(6) = '1' AND OE_nwv = '1')),
               1 => (InputChangeTime   => Byte1(6)'LAST_EVENT,
                     PathDelay         => tpd_OE_SDR0,
                     PathCondition     => TRUE ),
               2 => (InputChangeTime   => OE_nwv'LAST_EVENT,
                     PathDelay         => tpd_OE_SDR0,
                     PathCondition     => TRUE ) ),
            GlitchData      => SDR14_GlitchData );

        VitalPathDelay01Z (
            OutSignal       =>  SDR15,
            OutSignalName   =>  "SDR15",
            OutTemp         =>  SDR15_zd,
            Paths           => (
               0 => (InputChangeTime   => BUFIN_ipd'LAST_EVENT,
                    PathDelay         => VitalExtendToFillDelay(tpd_BUFIN_SDR0),
                     PathCondition     => (Byte1(7) = '1' AND OE_nwv = '1')),
               1 => (InputChangeTime   => Byte1(7)'LAST_EVENT,
                     PathDelay         => tpd_OE_SDR0,
                     PathCondition     => TRUE ),
               2 => (InputChangeTime   => OE_nwv'LAST_EVENT,
                     PathDelay         => tpd_OE_SDR0,
                     PathCondition     => TRUE ) ),
            GlitchData      => SDR15_GlitchData );

        VitalPathDelay01Z (
            OutSignal       =>  SDR16,
            OutSignalName   =>  "SDR16",
            OutTemp         =>  SDR16_zd,
            Paths           => (
               0 => (InputChangeTime   => BUFIN_ipd'LAST_EVENT,
                    PathDelay         => VitalExtendToFillDelay(tpd_BUFIN_SDR0),
                     PathCondition     => (Byte2(6) = '1' AND OE_nwv = '1')),
               1 => (InputChangeTime   => Byte2(6)'LAST_EVENT,
                     PathDelay         => tpd_OE_SDR0,
                     PathCondition     => TRUE ),
               2 => (InputChangeTime   => OE_nwv'LAST_EVENT,
                     PathDelay         => tpd_OE_SDR0,
                     PathCondition     => TRUE ) ),
            GlitchData      => SDR16_GlitchData );

        VitalPathDelay01Z (
            OutSignal       =>  SDR17,
            OutSignalName   =>  "SDR17",
            OutTemp         =>  SDR17_zd,
            Paths           => (
               0 => (InputChangeTime   => BUFIN_ipd'LAST_EVENT,
                    PathDelay         => VitalExtendToFillDelay(tpd_BUFIN_SDR0),
                     PathCondition     => (Byte2(7) = '1' AND OE_nwv = '1')),
               1 => (InputChangeTime   => Byte2(7)'LAST_EVENT,
                     PathDelay         => tpd_OE_SDR0,
                     PathCondition     => TRUE ),
               2 => (InputChangeTime   => OE_nwv'LAST_EVENT,
                     PathDelay         => tpd_OE_SDR0,
                     PathCondition     => TRUE ) ),
            GlitchData      => SDR17_GlitchData );


    END PROCESS VitalBehavior1;

    VitalBehavior2 : PROCESS (SDATA_ipd, SCLK_ipd)

        -- Type definitions
        TYPE I2C_State IS (Stop,
                           Start,
                           Ignore,
                           Read
                          );

        VARIABLE State     : I2C_State;
        VARIABLE BitCount  : natural range 0 to 7;
        VARIABLE ByteCount : natural range 0 to 4;
        VARIABLE TmpByte   : std_logic_vector(7 downto 0);
        VARIABLE SDATA_nwv : X01;
        VARIABLE SCLK_nwv  : X01;
        VARIABLE Ack       : boolean := false;

        -- Timing Check Variables
        VARIABLE Tviol_SDATA_SCLK  : X01 := '0';
        VARIABLE TD_SDATA_SCLK     : VitalTimingDataType;

        VARIABLE Pviol_SCLK        : X01 := '0';
        VARIABLE PD_SCLK           : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Violation         : X01 := '0';

        -- Functionality Results Variables
        VARIABLE SDATA_zd          : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE SDATA_GlitchData  : VitalGlitchDataType;


    BEGIN
        SDATA_nwv := to_X01(SDATA_ipd);
        SCLK_nwv := to_X01(SCLK);

        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalSetupHoldCheck (
                TestSignal      => SDATA_ipd,
                TestSignalName  => "SDATA",
                RefSignal       => SCLK_ipd,
                RefSignalName   => "SCLK",
                SetupHigh       => tsetup_SDATA_SCLK,
                SetupLow        => tsetup_SDATA_SCLK,
                HoldHigh        => thold_SDATA_SCLK,
                HoldLow         => thold_SDATA_SCLK,
                CheckEnabled    => TRUE,
                RefTransition   => '*',
                HeaderMsg       => InstancePath & "/cy2318anz",
                TimingData      => TD_SDATA_SCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_SDATA_SCLK
            );

            VitalPeriodPulseCheck (
                TestSignal      => SCLK_ipd,
                TestSignalName  => "SCLK",
                Period          => tperiod_SCLK_posedge,
                PulseWidthHigh  => tpw_SCLK_posedge,
                PulseWidthLow   => tpw_SCLK_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & "/cy2318anz",
                PeriodData      => PD_SCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_SCLK
            );

        END IF;

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Violation := Tviol_SDATA_SCLK OR Pviol_SCLK;
        ASSERT Violation = '0'
        REPORT InstancePath & " control registers may be" &
                            " incorret due to I2C timing violation(s)"
        SEVERITY Warning;

        IF (falling_edge(SDATA_ipd) AND SCLK_ipd'stable AND SCLK_nwv = '1') THEN
            State := Start;
            BitCount := 0;
            ByteCount := 0;
        ELSIF (rising_edge(SDATA_ipd) AND SCLK_ipd'stable AND SCLK_nwv = '1') 
            THEN
            State := Stop;
        END IF;

        IF (rising_edge(SCLK_ipd) AND Ack = false) THEN
            CASE State IS
                WHEN Start =>
                    TmpByte(BitCount) := SDATA_nwv;
                    IF (BitCount < 7) THEN
                        BitCount := BitCount + 1;
                    ELSIF (TmpByte = Address) THEN
                        State := Read;
                        Ack := true;
                    ELSE
                        State := Ignore;
                    END IF;

                WHEN Read =>
                    CASE ByteCount IS
                        WHEN 0 | 1 =>      -- throw away first 2 bytes
                            IF (BitCount < 7) THEN
                                BitCount := BitCount + 1;
                            ELSE
                                ByteCount := ByteCount + 1;
                                Ack := true;
                            END IF;

                        WHEN 2 =>
                            Byte0(BitCount) <= SDATA_nwv;
                            IF (BitCount < 7) THEN
                                BitCount := BitCount + 1;
                            ELSE
                                ByteCount := ByteCount + 1;
                                Ack := true;
                            END IF;

                        WHEN 3 =>
                            Byte1(BitCount) <= SDATA_nwv;
                            IF (BitCount < 7) THEN
                                BitCount := BitCount + 1;
                            ELSE
                                ByteCount := ByteCount + 1;
                                Ack := true;
                            END IF;

                        WHEN 4 =>
                            Byte2(BitCount) <= SDATA_nwv;
                            IF (BitCount < 7) THEN
                                BitCount := BitCount + 1;
                            ELSE
                                Ack := true;
                            END IF;
                    END CASE;

                WHEN Stop =>
                    NULL;

                WHEN Ignore =>
                    NULL;

           END CASE;
        END IF;

        IF (falling_edge(SCLK_ipd) AND Ack = true) THEN
            IF (SDATA_zd = '0') THEN
                Ack := false;
                SDATA_zd := 'Z';
                BitCount := 0;
            ELSE
                SDATA_zd := '0';
            END IF;
        END IF;
        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       =>  SDATA,
            OutSignalName   =>  "SDATA",
            OutTemp         =>  SDATA_zd,
            Paths           => (
               0 => (InputChangeTime   => SCLK_ipd'LAST_EVENT,
                     PathDelay         => tpd_SCLK_SDATA,
                     PathCondition     => TRUE ) ),
            GlitchData      => SDATA_GlitchData );


    END PROCESS VitalBehavior2;

END vhdl_behavioral;