cy2318anz.vhd

Vhdl cod for a clock for sp3e

--------------------------------------------------------------------------------
--  File Name: cy2318anz.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2000-2008 Free Model Foundry; http://www.FreeModelFoundry.com/
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    00 JUL 18   Initial release
--    V1.1    R. Munden    02 MAR 30   Corrected for ModelSim 5.6
--    V1.2    R. Munden    08 APR 22   Corrected typo in path delays
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    CLOCK
--  Technology: LVTTL
--  Part:       CY2318ANZ
-- 
--  Description: Clock Buffer with 3-State Control and I2C
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY cy2318anz IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_BUFIN               : VitalDelayType01 := VitalZeroDelay01;
        tipd_SDATA               : VitalDelayType01 := VitalZeroDelay01;
        tipd_SCLK                : VitalDelayType01 := VitalZeroDelay01;
        tipd_OE                  : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_BUFIN_SDR0           : VitalDelayType01 := UnitDelay01;
        tpd_OE_SDR0              : VitalDelayType01Z := UnitDelay01Z;
        tpd_SCLK_SDATA           : VitalDelayType01Z := UnitDelay01Z;
        -- tsetup values: setup times
        tsetup_SDATA_SCLK        : VitalDelayType := UnitDelay;
        -- thold values: hold times
        thold_SDATA_SCLK         : VitalDelayType := UnitDelay;
        -- tpw values: pulse widths
        tpw_BUFIN_posedge        : VitalDelayType := UnitDelay;
        tpw_BUFIN_negedge        : VitalDelayType := UnitDelay;
        tpw_SCLK_posedge         : VitalDelayType := UnitDelay;
        tpw_SCLK_negedge         : VitalDelayType := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_BUFIN_posedge    : VitalDelayType := UnitDelay;
        tperiod_SCLK_posedge     : VitalDelayType := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        BUFIN           : IN    std_ulogic := 'U';
        OE              : IN    std_ulogic := 'U';
        SDATA           : INOUT std_ulogic := 'H';
        SCLK            : IN    std_ulogic := 'H';
        SDR0            : OUT   std_ulogic := 'U';
        SDR1            : OUT   std_ulogic := 'U';
        SDR2            : OUT   std_ulogic := 'U';
        SDR3            : OUT   std_ulogic := 'U';
        SDR4            : OUT   std_ulogic := 'U';
        SDR5            : OUT   std_ulogic := 'U';
        SDR6            : OUT   std_ulogic := 'U';
        SDR7            : OUT   std_ulogic := 'U';
        SDR8            : OUT   std_ulogic := 'U';
        SDR9            : OUT   std_ulogic := 'U';
        SDR10           : OUT   std_ulogic := 'U';
        SDR11           : OUT   std_ulogic := 'U';
        SDR12           : OUT   std_ulogic := 'U';
        SDR13           : OUT   std_ulogic := 'U';
        SDR14           : OUT   std_ulogic := 'U';
        SDR15           : OUT   std_ulogic := 'U';
        SDR16           : OUT   std_ulogic := 'U';
        SDR17           : OUT   std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of cy2318anz : ENTITY IS TRUE;
END cy2318anz;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of cy2318anz IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL BUFIN_ipd         : std_ulogic := 'U';
    SIGNAL OE_ipd            : std_ulogic := 'U';
    SIGNAL SDATA_ipd         : std_ulogic := 'U';
    SIGNAL SCLK_ipd          : std_ulogic := 'U';
    SIGNAL OE_nwv            : X01 := 'X';
    SIGNAL Byte0             : std_logic_vector(7 downto 0) := (OTHERS => '1'); 
    SIGNAL Byte1             : std_logic_vector(7 downto 0) := (OTHERS => '1'); 
    SIGNAL Byte2             : std_logic_vector(7 downto 0) := (OTHERS => '1'); 
    CONSTANT Address         : std_logic_vector(7 downto 0) := "01001011"; 

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (BUFIN_ipd, BUFIN, tipd_BUFIN);
        w_2 : VitalWireDelay (OE_ipd, OE, tipd_OE);
        w_3 : VitalWireDelay (SDATA_ipd, SDATA, tipd_SDATA);
        w_4 : VitalWireDelay (SCLK_ipd, SCLK, tipd_SCLK);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent procedure calls
    ----------------------------------------------------------------------------

    OE_nwv <= to_X01(OE_ipd);

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
    VitalBehavior1 : PROCESS (BUFIN_ipd, OE_nwv, Byte0, Byte1, Byte2)

        -- Timing Check Variables
        VARIABLE Pviol_BUFIN       : X01 := '0';
        VARIABLE PD_BUFIN          : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Violation         : X01 := '0';

        -- Functionality Results Variables
        VARIABLE SDR0_zd           : std_ulogic;
        VARIABLE SDR1_zd           : std_ulogic;
        VARIABLE SDR2_zd           : std_ulogic;
        VARIABLE SDR3_zd           : std_ulogic;
        VARIABLE SDR4_zd           : std_ulogic;
        VARIABLE SDR5_zd           : std_ulogic;
        VARIABLE SDR6_zd           : std_ulogic;
        VARIABLE SDR7_zd           : std_ulogic;
        VARIABLE SDR8_zd           : std_ulogic;
        VARIABLE SDR9_zd           : std_ulogic;
        VARIABLE SDR10_zd          : std_ulogic;
        VARIABLE SDR11_zd          : std_ulogic;
        VARIABLE SDR12_zd          : std_ulogic;
        VARIABLE SDR13_zd          : std_ulogic;
        VARIABLE SDR14_zd          : std_ulogic;
        VARIABLE SDR15_zd          : std_ulogic;
        VARIABLE SDR16_zd          : std_ulogic;
        VARIABLE SDR17_zd          : std_ulogic;

        -- Output Glitch Detection Variables
        VARIABLE SDR0_GlitchData   : VitalGlitchDataType;
        VARIABLE SDR1_GlitchData   : VitalGlitchDataType;
        VARIABLE SDR2_GlitchData   : VitalGlitchDataType;
        VARIABLE SDR3_GlitchData   : VitalGlitchDataType;
        VARIABLE SDR4_GlitchData   : VitalGlitchDataType;
        VARIABLE SDR5_GlitchData   : VitalGlitchDataType;
        VARIABLE SDR6_GlitchData   : VitalGlitchDataType;
        VARIABLE SDR7_GlitchData   : VitalGlitchDataType;
        VARIABLE SDR8_GlitchData   : VitalGlitchDataType;
        VARIABLE SDR9_GlitchData   : VitalGlitchDataType;
        VARIABLE SDR10_GlitchData  : VitalGlitchDataType;
        VARIABLE SDR11_GlitchData  : VitalGlitchDataType;
        VARIABLE SDR12_GlitchData  : VitalGlitchDataType;
        VARIABLE SDR13_GlitchData  : VitalGlitchDataType;
        VARIABLE SDR14_GlitchData  : VitalGlitchDataType;
        VARIABLE SDR15_GlitchData  : VitalGlitchDataType;
        VARIABLE SDR16_GlitchData  : VitalGlitchDataType;
        VARIABLE SDR17_GlitchData  : VitalGlitchDataType;

    BEGIN
        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalPeriodPulseCheck (
                TestSignal      => BUFIN_ipd,
                TestSignalName  => "BUFIN_ipd",
                Period          => tperiod_BUFIN_posedge,
                PulseWidthHigh  => tpw_BUFIN_posedge,
                PulseWidthLow   => tpw_BUFIN_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & "/cy2318anz",
                PeriodData      => PD_BUFIN,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_BUFIN
            );

        END IF;

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Violation := Pviol_BUFIN;

        IF (Violation = '0') THEN
            SDR0_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte0(0) AND OE_nwv );
            SDR1_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte0(1) AND OE_nwv );
            SDR2_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte0(2) AND OE_nwv );
            SDR3_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte0(3) AND OE_nwv );
            SDR4_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte0(4) AND OE_nwv );
            SDR5_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte0(5) AND OE_nwv );
            SDR6_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte0(6) AND OE_nwv );
            SDR7_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte0(7) AND OE_nwv );
            SDR8_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte1(0) AND OE_nwv );
            SDR9_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte1(1) AND OE_nwv );
            SDR10_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte1(2) AND OE_nwv );
            SDR11_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte1(3) AND OE_nwv );
            SDR12_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte1(4) AND OE_nwv );
            SDR13_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte1(5) AND OE_nwv );
            SDR14_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte1(6) AND OE_nwv );
            SDR15_zd := VitalBUFIF1 (data => BUFIN_ipd,
                                    enable => Byte1(7) AND OE_nwv );