📄 i2c_drive_ms_pkg.vhd
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WHEN 2 => -- hardware master (10bit address) -- program dump address (address hardware master will send data to) REPORT "Set dump address, hw master has 10 bit address, "& "master writes dump address to hw master(slave)"; -- slv22 has 10 bit addr command_seq(1) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(2) :=(dev0 ,write ,slv22,0,0 ns); -- write dump address command_seq(3) :=(dev0 ,write ,slv1_w,0,0 ns); command_seq(4) :=(all_dev ,idle ,0,0,t+200 us); command_seq(5):=(all_dev ,done ,0,0,0 ns); --WHEN 3 => see TC4.1 dev23 -- set dump address using general call procedure --WHEN 3 => --set dump address in HS mode (7 bit addressing) --WHEN 4 => --set dump address in HS mode (10 bit addressing) WHEN OTHERS => NULL; END CASE;-------------------------------------------------- GENERAL CALL-- TSs 4-5------------------------------------------------ WHEN 4 => -- GENERAL CALL PORCEDURE TO SLAVES CASE Testcase IS WHEN 1 => REPORT "General call procedure, second byte is 0x04"; command_seq(1) :=(dev0 ,req_bus ,gen_call,0,0 ns); command_seq(2) :=(dev0 ,write ,16#04#,0,0 ns); command_seq(3) :=(all_dev ,idle ,0,0,t+200 us); command_seq(4) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => REPORT "General call procedure, second byte is 0x06"; command_seq(1) :=(dev0 ,req_bus ,gen_call,0,0 ns); command_seq(2) :=(dev0 ,write ,16#06#,0,0 ns); command_seq(3) :=(all_dev ,idle ,0,0,t+200 us); command_seq(4) :=(all_dev ,done ,0,0,0 ns); WHEN 3 => REPORT "New transaction after GENERAL CALL procedure"; command_seq(1) :=(dev0 ,req_bus ,gen_call,0,0 ns); command_seq(2) :=(dev0 ,write ,16#06#,0,0 ns); command_seq(3) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(4) :=(dev0 ,write ,16#06#,0,0 ns); command_seq(5) :=(all_dev ,idle ,0,0,t+400 us); command_seq(6) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => null; END CASE; WHEN 5 => -- GENERAL CALL PROCEDURE FROM HARDWARE MASTER CASE Testcase IS -- byte_to_write field is ignored in req_bus and first write commands, -- it is always set "00000000" and hardware address -- in model when hardware master requests bus WHEN 1 => REPORT "General call procedure from hw master device20, master terminates write"; -- dev20 is hardware master, dev0 should listen to it command_seq(1) :=(dev20 ,req_bus ,16#01#,0,0 ns);-- gen_call command_seq(2) :=(dev20 ,write ,16#00#,0,0 ns);-- slv20_r -- byte_to_write field is not ignored any more command_seq(3) :=(dev20 ,write ,16#06#,0,0 ns); command_seq(4) :=(dev20 ,write ,16#07#,0,0 ns); command_seq(5) :=(dev20 ,write ,16#08#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+400 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- hardware master dev20 REPORT "General call procedure from hw master device20, slave terminates write"; command_seq(1) :=(dev20 ,req_bus ,gen_call,0,0 ns); command_seq(2) :=(dev20 ,write ,slv20_r,0,0 ns); -- byte_to_write field is not ignored any more command_seq(3) :=(dev20 ,write ,16#09#,0,0 ns); command_seq(4) :=(dev20 ,write ,16#0A#,0,0 ns); command_seq(5) :=(dev1 ,idle ,0,0,t+100 us); command_seq(6) :=(dev1 ,dis_sl_resp ,0,0,50 us); command_seq(7) :=(all_dev ,idle ,0,0,t+400 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 3 => REPORT "General call procedure from hw master device21, master terminates write"; -- general call procedure hw master dev21 command_seq(1) :=(dev21 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev21 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev21 ,write ,16#11#,0,0 ns); command_seq(4) :=(dev21 ,write ,16#12#,0,0 ns); command_seq(5) :=(dev21 ,write ,16#13#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+400 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 4 => REPORT "General call procedure from hw master device21, slave terminates write"; -- general call procedure hw master dev21 command_seq(1) :=(dev21 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev21 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev21 ,write ,16#01#,0,0 ns); command_seq(4) :=(dev21 ,write ,16#14#,0,0 ns); command_seq(5) :=(dev1 ,idle ,0,0,t+100 us); command_seq(6) :=(dev1 ,dis_sl_resp ,0,0,50 us); command_seq(7) :=(all_dev ,idle ,0,0,t+400 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 5 => REPORT "General call procedure from hw master device22, master terminates write"; -- general call procedure hw master dev22 command_seq(1) :=(dev22 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev22 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev22 ,write ,16#21#,0,0 ns); command_seq(4) :=(dev22 ,write ,16#22#,0,0 ns); command_seq(5) :=(dev22 ,write ,16#23#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+400 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 6 => REPORT "General call procedure from hw master device22, slave terminates write"; -- general call procedure hw master dev22 command_seq(1) :=(dev22 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev22 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev22 ,write ,16#24#,0,0 ns); command_seq(4) :=(dev22 ,write ,16#25#,0,0 ns); command_seq(5) :=(dev1 ,idle ,0,0,t+100 us); command_seq(6) :=(dev1 ,dis_sl_resp ,0,0,50 us); command_seq(7) :=(all_dev ,idle ,0,0,t+400 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN 7 => REPORT "General call procedure from hw master device23, master terminates write"; -- general call procedure hw master dev23 command_seq(1) :=(dev23 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev23 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev23 ,write ,16#31#,0,0 ns); command_seq(4) :=(dev23 ,write ,16#32#,0,0 ns); command_seq(5) :=(dev23 ,write ,16#33#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+400 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN 8 => REPORT "General call procedure from hw master device23, slave terminates write"; -- general call procedure hw master dev23 command_seq(1) :=(dev23 ,req_bus ,16#00#,0,0 ns); command_seq(2) :=(dev23 ,write ,16#00#,0,0 ns); -- sends data to dev1 command_seq(3) :=(dev23 ,write ,16#34#,0,0 ns); command_seq(4) :=(dev23 ,write ,16#35#,0,0 ns); command_seq(5) :=(dev1 ,idle ,0,0,t+100 us); command_seq(6) :=(dev1 ,dis_sl_resp ,0,0,50 us); command_seq(7) :=(all_dev ,idle ,0,0,t+400 us); command_seq(8) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN 6 => -- NEGATIVE AFTER HARDWARE MASTER IS INITIALIZED IT DOES NOT ACT AS SLAVE CASE Testcase IS WHEN 1 => -- hardware master (7bit address) REPORT "Negative, after hw master is initialized it can not act as a slave"; --master 21 -- old hw master slave addr command_seq(1) :=(dev0 ,req_bus ,slv21_w,0,0 ns); command_seq(2) :=(dev0 ,req_bus ,slv21_r,0,0 ns); --master 22 -- old hw master slave addr command_seq(3) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(4) :=(dev0 ,write ,slv22,0,0 ns); -- new hw master slave addr 21, 22, 23 command_seq(5) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(6) :=(dev0 ,req_bus ,slv1_r,1,0 ns); -- general call command_seq(7) :=(dev0 ,req_bus ,gen_call,0,0 ns); -- hs mode command_seq(8) :=(all_dev ,idle ,0,0,t+700 us); command_seq(9) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE;------------------------------READ/WRITE TRANSACTIONS-- TCs 7 - 9---------------------------- WHEN 7 => -- INITAIAL BYTE, bus is free -- master requests bus, output initial byte -- terminates transaction after initial byte CASE Testcase IS WHEN 1 => -- master addresses itself REPORT "initial byte test, trans. write, slave response "; command_seq(1) :=(dev0 ,req_bus ,slv0_w,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 ns); WHEN 2 => -- master addresses itself REPORT "initial byte test, trans. read, slave response "; command_seq(1) :=(dev0 ,req_bus ,slv0_r,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 us); WHEN 3 => -- master addresses another slave REPORT "initial byte test, trans. write, slave response "; command_seq(1) :=(dev0 ,req_bus ,slv1_w,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 ns); WHEN 4 => -- master addresses another slave REPORT "initial byte test, trans. read, slave response "; command_seq(1) :=(dev0 ,req_bus ,slv1_r,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 us); WHEN 5 => -- master addresses non existing slave REPORT "initial byte test, trans. write, no slave response "; command_seq(1) :=(dev0 ,req_bus ,no_slv_w,0,0 ns); command_seq(2) :=(all_dev ,idle ,0,0,t); command_seq(3) :=(all_dev ,done ,0,0,0 us); WHEN 6 => -- master addresses non existing slave⌨️ 快捷键说明
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