📄 i2c_drive_ms_pkg.vhd
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---------------------------------------------------------------------------------------------------------------------------------------------------------- Copyright (C) 2004 Free Model Foundry; http://www.FreeModelFoundry.com/---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.----------------------------------------------------------------------------- -- -- Company : HDL Design House, Serbia and Montenegro-- Project : PSPP1284-- Module : i2c_drive_ms_pkg---- Date : 12.03.2004-- Ver. : 1.0---- Author : J.Bogosavljevic-- Email : j-bogosavljevic@hdl-dh.com-- Phone : +381 11 344 23 59---- Customer :--------------------------------------------------------------------------------- Functional description of the module:-- i2c_drive_ms_pkg generates commands that drive i2c masters and-- slaves. Used to simulate devices connected to i2c bus over i2c bus-- interface------------------------------------------------------------------------------------------------------------------------------------------------------------LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE STD.textio.ALL;LIBRARY FMF; USE FMF.gen_utils.all; USE FMF.conversions.all;--------------------------------------------------------------------------------- ENTITY DECLARATION-------------------------------------------------------------------------------PACKAGE i2c_drive_ms_pkg IS --------------------------------------------------------------------------- --TC type --------------------------------------------------------------------------- TYPE TC_type IS RECORD SERIES : NATURAL RANGE 1 TO 30; TESTCASE : NATURAL RANGE 1 TO 15; END RECORD; --------------------------------------------------------------------------- -- commands to the device --------------------------------------------------------------------------- TYPE CMD_TYPE IS ( done, idle, none, req_bus, write, read, delay_clk, dis_sl_resp ); --------------------------------------------------------------------------- -- --------------------------------------------------------------------------- TYPE cmd_rec IS RECORD device_id : STRING(11 downto 1); cmd : cmd_type; wr_byte : NATURAL; rd_byte_num : NATURAL ; wtime : time; --valid with wt cmd END RECORD; --number of testcases pre testseriese TYPE tc_list IS ARRAY (1 TO 30) OF NATURAL; CONSTANT tc : tc_list := --0 1 2 3 --1-2-3-4-5-6-7-8-9-0-1-2-3-4-5-6-7-8-9-0-1-2-3-4-5-6-7-8-9-0 (1,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9,9); --TC command sequence TYPE cmd_seq_type IS ARRAY(0 TO 200) OF cmd_rec; SHARED VARIABLE t :TIME := 200 us; --------------------------------------------------------------------------- --PUBLIC --PROCEDURE to generate command sequence --------------------------------------------------------------------------- PROCEDURE Generate_TC ( Device_id : IN STRING ; Series : IN NATURAL RANGE 1 TO 30; TestCase : IN NATURAL RANGE 1 TO 30; curr_time : IN TIME; command_seq : OUT cmd_seq_type ); END PACKAGE i2c_drive_ms_pkg;PACKAGE BODY i2c_drive_ms_pkg IS --------------------------------------------------------------------------- --Public PROCEDURE to generate command sequence --------------------------------------------------------------------------- PROCEDURE Generate_TC ( device_id : IN STRING ; Series : IN NATURAL RANGE 1 TO 30; TestCase : IN NATURAL RANGE 1 TO 30; curr_time : IN TIME; command_seq : OUT cmd_seq_type ) IS VARIABLE len : NATURAL := 11; VARIABLE all_dev : STRING(len downto 1); VARIABLE dev0 : STRING(len downto 1) := "U00_i2c_dev"; VARIABLE dev1 : STRING(len downto 1) := "U01_i2c_dev"; VARIABLE dev2 : STRING(len downto 1) := "U02_i2c_dev"; -- hardware masters VARIABLE dev20 : STRING(len downto 1) := "U20_i2c_dev"; VARIABLE dev21 : STRING(len downto 1) := "U21_i2c_dev"; VARIABLE dev22 : STRING(len downto 1) := "U22_i2c_dev"; VARIABLE dev23 : STRING(len downto 1) := "U23_i2c_dev"; -- 7 bit addressing VARIABLE slv0_r : NATURAL := 2#0101_0101#; VARIABLE slv0_w : NATURAL := 2#0101_0100#; VARIABLE slv1_r : NATURAL := 2#0101_0001#;--2#0101_0111#; VARIABLE slv1_w : NATURAL := 2#0101_0000#;--2#0101_0110#; -- 10 bit addressing VARIABLE slv2 : NATURAL := 2#1010_1000#;--11 "11_1010_1000" VARIABLE slv3 : NATURAL := 2#1010_1000#;--10 "10_1010_1000" -- hardware master VARIABLE slv22 : NATURAL := 2#0010_0010#;--22 "11_0010_0010" -- hardware masters VARIABLE slv20_r : NATURAL := 2#0101_0111#; -- hardware master that is in slave receive mode after system reset VARIABLE slv21_w : NATURAL := 2#0101_1000#; VARIABLE slv21_r : NATURAL := 2#0101_1001#; -- no slave should have this address VARIABLE no_slv_r : NATURAL := 2#1110_0001#; VARIABLE no_slv_w : NATURAL := 2#1110_0000#; -- general call VARIABLE gen_call : NATURAL := 2#0000_0000#; VARIABLE start : NATURAL := 2#0000_0001#; VARIABLE t : TIME := 200 us; VARIABLE t_curr : TIME := 0 ns; BEGIN t := curr_time + t; t_curr := curr_time; FOR i IN 1 TO 200 LOOP --device_id, cmd, wr_byte, rd_byte_num ,wtime command_seq(i) :=(all_dev,done,0,0,0 ns); END LOOP; all_dev(7 downto 1) := "all_dev"; IF device_id = dev0 THEN REPORT "------------------------------------------------------" ; REPORT "------------------------------------------------------" ; REPORT "TestSeries : "& to_int_str(Series )&" "& "TC : "& to_int_str(TestCase); REPORT "------------------------------------------------------" ; END IF; CASE Series IS WHEN 1 => -- POWER UP, bus is free REPORT "Power up, bus is free"; --device_id, cmd, wr_byte, rd_byte_num ,wtime command_seq(1) :=(all_dev ,idle ,0,0,t); command_seq(2) :=(all_dev ,done ,0,0,0 ns);-------------------------------------------------- HARDWARE MASTER TEST SERIES-- GENERAL CALL-- TSs 2-6------------------------------------------------ WHEN 2 => -- NEGATIVE HARDWARE MASTER CAN NOT BE READ CASE Testcase IS WHEN 1 => REPORT "Negative, hardware master can not be read"; -- read request to hw master 20; hw master is not slave command_seq(1) :=(dev0 ,req_bus ,slv20_r,0,0 ns); -- read request to hw master 21; hw master is slave command_seq(2) :=(dev0 ,req_bus ,slv21_r,0,0 ns); -- read request to hw master 22; hw master 10bit addr, is slave command_seq(3) :=(dev0 ,req_bus ,2#1111_0110#,0,0 ns); command_seq(4) :=(dev0 ,write ,slv22,0,0 ns); command_seq(5) :=(dev0 ,req_bus ,2#1111_0111#,0,0 ns); command_seq(6) :=(all_dev ,idle ,0,0,t+600 us); command_seq(7) :=(all_dev ,done ,0,0,0 ns); WHEN OTHERS => NULL; END CASE; WHEN 3 => -- SETTING ADDRESS DATA WILL BE SENT TO -- (DUMP ADDRESS) FOR HARDWARE MASTER THAT -- IS IN SLAVE RECEIVE MODE AFTER SYSTEM RESET CASE Testcase IS WHEN 1 => -- hardware master (7bit address) -- program dump address (address hardware master will send data to) REPORT "Set dump address, hw master has 7 bit address, "& "master writes dump address to hw master(slave)"; command_seq(1) :=(dev0 ,req_bus ,slv21_w,0,0 ns); -- dump adress is slave2 address command_seq(2) :=(dev0 ,write ,slv1_w,0,0 ns); command_seq(3) :=(all_dev ,idle ,0,0,t); command_seq(4) :=(all_dev ,done ,0,0,0 ns);
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