m5stats.txt

来自「linux下基于c++的处理器仿真平台。具有处理器流水线」· 文本 代码 · 共 577 行 · 第 1/5 页

cpu0.icache.protocol.snoop_readex_shared            0                       # readEx snoops on shared blocks
cpu0.icache.protocol.snoop_upgrade_owned            0                       # upgrade snoops on owned blocks
cpu0.icache.protocol.snoop_upgrade_shared            0                       # upgradee snoops on shared blocks
cpu0.icache.protocol.snoop_writeinv_exclusive            0                       # WriteInvalidate snoops on exclusive blocks
cpu0.icache.protocol.snoop_writeinv_invalid            0                       # WriteInvalidate snoops on invalid blocks
cpu0.icache.protocol.snoop_writeinv_modified            0                       # WriteInvalidate snoops on modified blocks
cpu0.icache.protocol.snoop_writeinv_owned            0                       # WriteInvalidate snoops on owned blocks
cpu0.icache.protocol.snoop_writeinv_shared            0                       # WriteInvalidate snoops on shared blocks
cpu0.icache.protocol.swpf_invalid                   0                       # soft prefetch misses to invalid blocks
cpu0.icache.protocol.write_invalid                  0                       # write misses to invalid blocks
cpu0.icache.protocol.write_owned                    0                       # write misses to owned blocks
cpu0.icache.protocol.write_shared                   0                       # write misses to shared blocks
cpu0.icache.read_accesses                    15634063                       # number of read accesses(hits+misses)
cpu0.icache.read_hits                        15631938                       # number of read hits
cpu0.icache.read_miss_rate                   0.000136                       # miss rate for read accesses
cpu0.icache.read_misses                          2125                       # number of read misses
cpu0.icache.replacements                         1183                       # number of replacements
cpu0.icache.sampled_refs                         2125                       # Sample count of references to valid blocks.
cpu0.icache.tagsinuse                      881.825632                       # Cycle average of tags in use
cpu0.icache.total_refs                       15631938                       # Total number of references to valid blocks.
cpu0.icache.warmup_cycle                            0                       # Cycle when the warmup percentage was hit.
cpu0.icache.writebacks                              0                       # number of writebacks
cpu0.idle_fraction                           0.000444                       # Percentage of idle cycles
cpu0.not_idle_fraction                       0.999556                       # Percentage of non-idle cycles
cpu0.numCycles                               15634063                       # number of cpu cycles simulated
cpu0.num_insts                               15634063                       # Number of instructions executed
cpu0.num_refs                                 2661969                       # Number of memory references
cpu1.dcache.avg_blocked_cycles_no_mshrs  <err: div-0>                       # average number of cycles each access was blocked
cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
cpu1.dcache.avg_refs                        40.604372                       # Average number of references to valid blocks.
cpu1.dcache.blocked_no_mshrs                        0                       # number of cycles access was blocked
cpu1.dcache.blocked_no_targets                      0                       # number of cycles access was blocked
cpu1.dcache.blocked_cycles_no_mshrs                 0                       # number of cycles access was blocked
cpu1.dcache.blocked_cycles_no_targets               0                       # number of cycles access was blocked
cpu1.dcache.cache_copies                            0                       # number of cache copies performed
cpu1.dcache.demand_accesses                   2467105                       # number of demand (read+write) accesses
cpu1.dcache.demand_avg_miss_latency                 0                       # average overall miss latency
cpu1.dcache.demand_hits                       2405808                       # number of demand (read+write) hits
cpu1.dcache.demand_miss_latency                     0                       # number of demand (read+write) miss cycles
cpu1.dcache.demand_miss_rate                 0.024846                       # miss rate for demand accesses
cpu1.dcache.demand_misses                       61297                       # number of demand (read+write) misses
cpu1.dcache.fast_writes                             0                       # number of fast writes performed
cpu1.dcache.overall_accesses                  2467105                       # number of overall (read+write) accesses
cpu1.dcache.overall_avg_miss_latency                0                       # average overall miss latency
cpu1.dcache.overall_hits                      2405808                       # number of overall hits
cpu1.dcache.overall_miss_latency                    0                       # number of overall miss cycles
cpu1.dcache.overall_miss_rate                0.024846                       # miss rate for overall accesses
cpu1.dcache.overall_misses                      61297                       # number of overall misses
cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu1.dcache.prefetcher.num_hwpf_evicted             0                       # number of hwpf removed due to no buffer left
cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
cpu1.dcache.prefetcher.num_hwpf_issued              0                       # number of hwpf issued
cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu1.dcache.protocol.hwpf_invalid                   0                       # hard prefetch misses to invalid blocks
cpu1.dcache.protocol.read_invalid               18075                       # read misses to invalid blocks
cpu1.dcache.protocol.snoop_inv_exclusive            0                       # Invalidate snoops on exclusive blocks
cpu1.dcache.protocol.snoop_inv_invalid              0                       # Invalidate snoops on invalid blocks
cpu1.dcache.protocol.snoop_inv_modified             0                       # Invalidate snoops on modified blocks
cpu1.dcache.protocol.snoop_inv_owned                0                       # Invalidate snoops on owned blocks
cpu1.dcache.protocol.snoop_inv_shared               0                       # Invalidate snoops on shared blocks
cpu1.dcache.protocol.snoop_read_exclusive            0                       # read snoops on exclusive blocks
cpu1.dcache.protocol.snoop_read_modified          621                       # read snoops on modified blocks
cpu1.dcache.protocol.snoop_read_owned               0                       # read snoops on owned blocks
cpu1.dcache.protocol.snoop_read_shared            148                       # read snoops on shared blocks
cpu1.dcache.protocol.snoop_readex_exclusive            0                       # readEx snoops on exclusive blocks
cpu1.dcache.protocol.snoop_readex_modified          176                       # readEx snoops on modified blocks
cpu1.dcache.protocol.snoop_readex_owned             0                       # readEx snoops on owned blocks
cpu1.dcache.protocol.snoop_readex_shared            3                       # readEx snoops on shared blocks
cpu1.dcache.protocol.snoop_upgrade_owned            0                       # upgrade snoops on owned blocks
cpu1.dcache.protocol.snoop_upgrade_shared          268                       # upgradee snoops on shared blocks
cpu1.dcache.protocol.snoop_writeinv_exclusive            0                       # WriteInvalidate snoops on exclusive blocks
cpu1.dcache.protocol.snoop_writeinv_invalid            0                       # WriteInvalidate snoops on invalid blocks
cpu1.dcache.protocol.snoop_writeinv_modified            0                       # WriteInvalidate snoops on modified blocks
cpu1.dcache.protocol.snoop_writeinv_owned            0                       # WriteInvalidate snoops on owned blocks
cpu1.dcache.protocol.snoop_writeinv_shared            0                       # WriteInvalidate snoops on shared blocks
cpu1.dcache.protocol.swpf_invalid                   0                       # soft prefetch misses to invalid blocks
cpu1.dcache.protocol.write_invalid              41660                       # write misses to invalid blocks
cpu1.dcache.protocol.write_owned                    0                       # write misses to owned blocks
cpu1.dcache.protocol.write_shared                1562                       # write misses to shared blocks
cpu1.dcache.read_accesses                     1993197                       # number of read accesses(hits+misses)
cpu1.dcache.read_hits                         1975122                       # number of read hits
cpu1.dcache.read_miss_rate                   0.009068                       # miss rate for read accesses
cpu1.dcache.read_misses                         18075                       # number of read misses
cpu1.dcache.replacements                        58275                       # number of replacements
cpu1.dcache.sampled_refs                        59288                       # Sample count of references to valid blocks.
cpu1.dcache.tagsinuse                      921.804871                       # Cycle average of tags in use
cpu1.dcache.total_refs                        2407352                       # Total number of references to valid blocks.
cpu1.dcache.warmup_cycle                      3310041                       # Cycle when the warmup percentage was hit.
cpu1.dcache.write_accesses                     473908                       # number of write accesses(hits+misses)
cpu1.dcache.write_hits                         430686                       # number of write hits
cpu1.dcache.write_miss_rate                  0.091203                       # miss rate for write accesses
cpu1.dcache.write_misses                        43222                       # number of write misses
cpu1.dcache.writebacks                              0                       # number of writebacks
cpu1.icache.avg_blocked_cycles_no_mshrs  <err: div-0>                       # average number of cycles each access was blocked
cpu1.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
cpu1.icache.avg_refs                     40732.537234                       # Average number of references to valid blocks.
cpu1.icache.blocked_no_mshrs                        0                       # number of cycles access was blocked
cpu1.icache.blocked_no_targets                      0                       # number of cycles access was blocked
cpu1.icache.blocked_cycles_no_mshrs                 0                       # number of cycles access was blocked
cpu1.icache.blocked_cycles_no_targets               0                       # number of cycles access was blocked
cpu1.icache.cache_copies                            0                       # number of cache copies performed
cpu1.icache.demand_accesses                  15315810                       # number of demand (read+write) accesses
cpu1.icache.demand_avg_miss_latency                 0                       # average overall miss latency
cpu1.icache.demand_hits                      15315434                       # number of demand (read+write) hits
cpu1.icache.demand_miss_latency                     0                       # number of demand (read+write) miss cycles
cpu1.icache.demand_miss_rate                 0.000025                       # miss rate for demand accesses
cpu1.icache.demand_misses                         376                       # number of demand (read+write) misses
cpu1.icache.fast_writes                             0                       # number of fast writes performed
cpu1.icache.overall_accesses                 15315810                       # number of overall (read+write) accesses
cpu1.icache.overall_avg_miss_latency                0                       # average overall miss latency
cpu1.icache.overall_hits                     15315434                       # number of overall hits
cpu1.icache.overall_miss_latency                    0                       # number of overall miss cycles