m5stats.txt
来自「linux下基于c++的处理器仿真平台。具有处理器流水线」· 文本 代码 · 共 577 行 · 第 1/5 页
TXT
577 行
cpu3.dcache.protocol.snoop_read_owned 0 # read snoops on owned blockscpu3.dcache.protocol.snoop_read_shared 333 # read snoops on shared blockscpu3.dcache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blockscpu3.dcache.protocol.snoop_readex_modified 148 # readEx snoops on modified blockscpu3.dcache.protocol.snoop_readex_owned 0 # readEx snoops on owned blockscpu3.dcache.protocol.snoop_readex_shared 0 # readEx snoops on shared blockscpu3.dcache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blockscpu3.dcache.protocol.snoop_upgrade_shared 553 # upgradee snoops on shared blockscpu3.dcache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blockscpu3.dcache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blockscpu3.dcache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blockscpu3.dcache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blockscpu3.dcache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blockscpu3.dcache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blockscpu3.dcache.protocol.write_invalid 41044 # write misses to invalid blockscpu3.dcache.protocol.write_owned 0 # write misses to owned blockscpu3.dcache.protocol.write_shared 1823 # write misses to shared blockscpu3.dcache.read_accesses 1999084 # number of read accesses(hits+misses)cpu3.dcache.read_hits 1980592 # number of read hitscpu3.dcache.read_miss_rate 0.009250 # miss rate for read accessescpu3.dcache.read_misses 18492 # number of read missescpu3.dcache.replacements 57831 # number of replacementscpu3.dcache.sampled_refs 58835 # Sample count of references to valid blocks.cpu3.dcache.tagsinuse 921.222709 # Cycle average of tags in usecpu3.dcache.total_refs 2415390 # Total number of references to valid blocks.cpu3.dcache.warmup_cycle 3341266 # Cycle when the warmup percentage was hit.cpu3.dcache.write_accesses 475855 # number of write accesses(hits+misses)cpu3.dcache.write_hits 432988 # number of write hitscpu3.dcache.write_miss_rate 0.090084 # miss rate for write accessescpu3.dcache.write_misses 42867 # number of write missescpu3.dcache.writebacks 0 # number of writebackscpu3.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blockedcpu3.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blockedcpu3.icache.avg_refs 42247.933884 # Average number of references to valid blocks.cpu3.icache.blocked_no_mshrs 0 # number of cycles access was blockedcpu3.icache.blocked_no_targets 0 # number of cycles access was blockedcpu3.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blockedcpu3.icache.blocked_cycles_no_targets 0 # number of cycles access was blockedcpu3.icache.cache_copies 0 # number of cache copies performedcpu3.icache.demand_accesses 15336363 # number of demand (read+write) accessescpu3.icache.demand_avg_miss_latency 0 # average overall miss latencycpu3.icache.demand_hits 15336000 # number of demand (read+write) hitscpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cyclescpu3.icache.demand_miss_rate 0.000024 # miss rate for demand accessescpu3.icache.demand_misses 363 # number of demand (read+write) missescpu3.icache.fast_writes 0 # number of fast writes performedcpu3.icache.overall_accesses 15336363 # number of overall (read+write) accessescpu3.icache.overall_avg_miss_latency 0 # average overall miss latencycpu3.icache.overall_hits 15336000 # number of overall hitscpu3.icache.overall_miss_latency 0 # number of overall miss cyclescpu3.icache.overall_miss_rate 0.000024 # miss rate for overall accessescpu3.icache.overall_misses 363 # number of overall missescpu3.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cachecpu3.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshrcpu3.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queuecpu3.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer leftcpu3.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identifiedcpu3.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issuedcpu3.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocatedcpu3.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual pagecpu3.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation timecpu3.icache.protocol.hwpf_invalid 0 # hard prefetch misses to invalid blockscpu3.icache.protocol.read_invalid 363 # read misses to invalid blockscpu3.icache.protocol.snoop_inv_exclusive 0 # Invalidate snoops on exclusive blockscpu3.icache.protocol.snoop_inv_invalid 0 # Invalidate snoops on invalid blockscpu3.icache.protocol.snoop_inv_modified 0 # Invalidate snoops on modified blockscpu3.icache.protocol.snoop_inv_owned 0 # Invalidate snoops on owned blockscpu3.icache.protocol.snoop_inv_shared 0 # Invalidate snoops on shared blockscpu3.icache.protocol.snoop_read_exclusive 0 # read snoops on exclusive blockscpu3.icache.protocol.snoop_read_modified 0 # read snoops on modified blockscpu3.icache.protocol.snoop_read_owned 0 # read snoops on owned blockscpu3.icache.protocol.snoop_read_shared 136 # read snoops on shared blockscpu3.icache.protocol.snoop_readex_exclusive 0 # readEx snoops on exclusive blockscpu3.icache.protocol.snoop_readex_modified 0 # readEx snoops on modified blockscpu3.icache.protocol.snoop_readex_owned 0 # readEx snoops on owned blockscpu3.icache.protocol.snoop_readex_shared 0 # readEx snoops on shared blockscpu3.icache.protocol.snoop_upgrade_owned 0 # upgrade snoops on owned blockscpu3.icache.protocol.snoop_upgrade_shared 0 # upgradee snoops on shared blockscpu3.icache.protocol.snoop_writeinv_exclusive 0 # WriteInvalidate snoops on exclusive blockscpu3.icache.protocol.snoop_writeinv_invalid 0 # WriteInvalidate snoops on invalid blockscpu3.icache.protocol.snoop_writeinv_modified 0 # WriteInvalidate snoops on modified blockscpu3.icache.protocol.snoop_writeinv_owned 0 # WriteInvalidate snoops on owned blockscpu3.icache.protocol.snoop_writeinv_shared 0 # WriteInvalidate snoops on shared blockscpu3.icache.protocol.swpf_invalid 0 # soft prefetch misses to invalid blockscpu3.icache.protocol.write_invalid 0 # write misses to invalid blockscpu3.icache.protocol.write_owned 0 # write misses to owned blockscpu3.icache.protocol.write_shared 0 # write misses to shared blockscpu3.icache.read_accesses 15336363 # number of read accesses(hits+misses)cpu3.icache.read_hits 15336000 # number of read hitscpu3.icache.read_miss_rate 0.000024 # miss rate for read accessescpu3.icache.read_misses 363 # number of read missescpu3.icache.replacements 14 # number of replacementscpu3.icache.sampled_refs 363 # Sample count of references to valid blocks.cpu3.icache.tagsinuse 298.404053 # Cycle average of tags in usecpu3.icache.total_refs 15336000 # Total number of references to valid blocks.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.cpu3.icache.writebacks 0 # number of writebackscpu3.idle_fraction 0.019477 # Percentage of idle cyclescpu3.not_idle_fraction 0.980523 # Percentage of non-idle cyclescpu3.numCycles 15336363 # number of cpu cycles simulatedcpu3.num_insts 15336363 # Number of instructions executedcpu3.num_refs 2552763 # Number of memory referencesdram.accesses 422202 # total number of accessesdram.bytes_requested 0 # total number of bytes requesteddram.bytes_sent 0 # total number of bytes sentdram.compressed_responses 0 # total number of accesses that are compressedhost_inst_rate 1697869 # Simulator instruction rate (inst/s)host_mem_usage 14304 # Number of bytes of host memory usedhost_seconds 36.31 # Real time elapsed on the hosthost_tick_rate 430755 # Simulator tick rate (ticks/s)sim_freq 200000000 # Frequency of simulated tickssim_insts 61649727 # Number of instructions simulatedsim_seconds 0.078205⌨️ 快捷键说明
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