prev_cmp_round.tan.qmsg

Simple 32 bit Floating point Multiplier

{ "Info" "ITDB_TSU_RESULT" "rndopt\[22\] rndip\[42\] en 26.304 ns register " "Info: tsu for register \"rndopt\[22\]\" (data pin = \"rndip\[42\]\", clock pin = \"en\") is 26.304 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "29.209 ns + Longest pin register " "Info: + Longest pin to register delay is 29.209 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rndip\[42\] 1 PIN PIN_11 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_11; Fanout = 7; PIN Node = 'rndip\[42\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rndip[42] } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.094 ns) + CELL(0.442 ns) 8.005 ns process0~15543 2 COMB LC_X13_Y17_N7 6 " "Info: 2: + IC(6.094 ns) + CELL(0.442 ns) = 8.005 ns; Loc. = LC_X13_Y17_N7; Fanout = 6; COMB Node = 'process0~15543'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.536 ns" { rndip[42] process0~15543 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.114 ns) 9.398 ns process0~160 3 COMB LC_X12_Y16_N1 7 " "Info: 3: + IC(1.279 ns) + CELL(0.114 ns) = 9.398 ns; Loc. = LC_X12_Y16_N1; Fanout = 7; COMB Node = 'process0~160'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.393 ns" { process0~15543 process0~160 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.650 ns) + CELL(0.292 ns) 11.340 ns process0~274 4 COMB LC_X14_Y15_N8 5 " "Info: 4: + IC(1.650 ns) + CELL(0.292 ns) = 11.340 ns; Loc. = LC_X14_Y15_N8; Fanout = 5; COMB Node = 'process0~274'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.942 ns" { process0~160 process0~274 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.335 ns) + CELL(0.292 ns) 12.967 ns process0~361 5 COMB LC_X15_Y14_N4 6 " "Info: 5: + IC(1.335 ns) + CELL(0.292 ns) = 12.967 ns; Loc. = LC_X15_Y14_N4; Fanout = 6; COMB Node = 'process0~361'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.627 ns" { process0~274 process0~361 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(0.292 ns) 14.867 ns process0~390 6 COMB LC_X12_Y16_N9 31 " "Info: 6: + IC(1.608 ns) + CELL(0.292 ns) = 14.867 ns; Loc. = LC_X12_Y16_N9; Fanout = 31; COMB Node = 'process0~390'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { process0~361 process0~390 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.456 ns) + CELL(0.114 ns) 18.437 ns process0~15784 7 COMB LC_X19_Y16_N9 1 " "Info: 7: + IC(3.456 ns) + CELL(0.114 ns) = 18.437 ns; Loc. = LC_X19_Y16_N9; Fanout = 1; COMB Node = 'process0~15784'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.570 ns" { process0~390 process0~15784 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.423 ns) + CELL(0.590 ns) 19.450 ns process0~15785 8 COMB LC_X19_Y16_N3 1 " "Info: 8: + IC(0.423 ns) + CELL(0.590 ns) = 19.450 ns; Loc. = LC_X19_Y16_N3; Fanout = 1; COMB Node = 'process0~15785'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.013 ns" { process0~15784 process0~15785 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.206 ns) + CELL(0.442 ns) 21.098 ns process0~15786 9 COMB LC_X19_Y15_N4 1 " "Info: 9: + IC(1.206 ns) + CELL(0.442 ns) = 21.098 ns; Loc. = LC_X19_Y15_N4; Fanout = 1; COMB Node = 'process0~15786'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.648 ns" { process0~15785 process0~15786 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.195 ns) + CELL(0.442 ns) 22.735 ns process0~15787 10 COMB LC_X19_Y14_N1 1 " "Info: 10: + IC(1.195 ns) + CELL(0.442 ns) = 22.735 ns; Loc. = LC_X19_Y14_N1; Fanout = 1; COMB Node = 'process0~15787'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.637 ns" { process0~15786 process0~15787 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.725 ns) + CELL(0.292 ns) 24.752 ns process0~15788 11 COMB LC_X15_Y13_N7 1 " "Info: 11: + IC(1.725 ns) + CELL(0.292 ns) = 24.752 ns; Loc. = LC_X15_Y13_N7; Fanout = 1; COMB Node = 'process0~15788'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.017 ns" { process0~15787 process0~15788 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.292 ns) 25.486 ns process0~15797 12 COMB LC_X15_Y13_N8 3 " "Info: 12: + IC(0.442 ns) + CELL(0.292 ns) = 25.486 ns; Loc. = LC_X15_Y13_N8; Fanout = 3; COMB Node = 'process0~15797'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.734 ns" { process0~15788 process0~15797 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.976 ns) + CELL(0.423 ns) 27.885 ns rndopt\[14\]~128 13 COMB LC_X21_Y11_N7 2 " "Info: 13: + IC(1.976 ns) + CELL(0.423 ns) = 27.885 ns; Loc. = LC_X21_Y11_N7; Fanout = 2; COMB Node = 'rndopt\[14\]~128'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.399 ns" { process0~15797 rndopt[14]~128 } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 27.963 ns rndopt\[15\]~129 14 COMB LC_X21_Y11_N8 2 " "Info: 14: + IC(0.000 ns) + CELL(0.078 ns) = 27.963 ns; Loc. = LC_X21_Y11_N8; Fanout = 2; COMB Node = 'rndopt\[15\]~129'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { rndopt[14]~128 rndopt[15]~129 } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.271 ns) 28.234 ns rndopt\[16\]~130 15 COMB LC_X21_Y11_N9 6 " "Info: 15: + IC(0.000 ns) + CELL(0.271 ns) = 28.234 ns; Loc. = LC_X21_Y11_N9; Fanout = 6; COMB Node = 'rndopt\[16\]~130'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.271 ns" { rndopt[15]~129 rndopt[16]~130 } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 28.370 ns rndopt\[21\]~135 16 COMB LC_X21_Y10_N4 2 " "Info: 16: + IC(0.000 ns) + CELL(0.136 ns) = 28.370 ns; Loc. = LC_X21_Y10_N4; Fanout = 2; COMB Node = 'rndopt\[21\]~135'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { rndopt[16]~130 rndopt[21]~135 } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 29.209 ns rndopt\[22\] 17 REG LC_X21_Y10_N5 1 " "Info: 17: + IC(0.000 ns) + CELL(0.839 ns) = 29.209 ns; Loc. = LC_X21_Y10_N5; Fanout = 1; REG Node = 'rndopt\[22\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { rndopt[21]~135 rndopt[22] } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.820 ns ( 23.35 % ) " "Info: Total cell delay = 6.820 ns ( 23.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "22.389 ns ( 76.65 % ) " "Info: Total interconnect delay = 22.389 ns ( 76.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "29.209 ns" { rndip[42] process0~15543 process0~160 process0~274 process0~361 process0~390 process0~15784 process0~15785 process0~15786 process0~15787 process0~15788 process0~15797 rndopt[14]~128 rndopt[15]~129 rndopt[16]~130 rndopt[21]~135 rndopt[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "29.209 ns" { rndip[42] rndip[42]~out0 process0~15543 process0~160 process0~274 process0~361 process0~390 process0~15784 process0~15785 process0~15786 process0~15787 process0~15788 process0~15797 rndopt[14]~128 rndopt[15]~129 rndopt[16]~130 rndopt[21]~135 rndopt[22] } { 0.000ns 0.000ns 6.094ns 1.279ns 1.650ns 1.335ns 1.608ns 3.456ns 0.423ns 1.206ns 1.195ns 1.725ns 0.442ns 1.976ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.442ns 0.114ns 0.292ns 0.292ns 0.292ns 0.114ns 0.590ns 0.442ns 0.442ns 0.292ns 0.292ns 0.423ns 0.078ns 0.271ns 0.136ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "en destination 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"en\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns en 1 CLK PIN_29 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 28; CLK Node = 'en'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns rndopt\[22\] 2 REG LC_X21_Y10_N5 1 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y10_N5; Fanout = 1; REG Node = 'rndopt\[22\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { en rndopt[22] } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { en rndopt[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { en en~out0 rndopt[22] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "29.209 ns" { rndip[42] process0~15543 process0~160 process0~274 process0~361 process0~390 process0~15784 process0~15785 process0~15786 process0~15787 process0~15788 process0~15797 rndopt[14]~128 rndopt[15]~129 rndopt[16]~130 rndopt[21]~135 rndopt[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "29.209 ns" { rndip[42] rndip[42]~out0 process0~15543 process0~160 process0~274 process0~361 process0~390 process0~15784 process0~15785 process0~15786 process0~15787 process0~15788 process0~15797 rndopt[14]~128 rndopt[15]~129 rndopt[16]~130 rndopt[21]~135 rndopt[22] } { 0.000ns 0.000ns 6.094ns 1.279ns 1.650ns 1.335ns 1.608ns 3.456ns 0.423ns 1.206ns 1.195ns 1.725ns 0.442ns 1.976ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.442ns 0.114ns 0.292ns 0.292ns 0.292ns 0.114ns 0.590ns 0.442ns 0.442ns 0.292ns 0.292ns 0.423ns 0.078ns 0.271ns 0.136ns 0.839ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { en rndopt[22] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { en en~out0 rndopt[22] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "en rndop\[17\] rndopt\[18\] 9.041 ns register " "Info: tco from clock \"en\" to destination pin \"rndop\[17\]\" through register \"rndopt\[18\]\" is 9.041 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "en source 2.942 ns + Longest register " "Info: + Longest clock path from clock \"en\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns en 1 CLK PIN_29 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 28; CLK Node = 'en'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns rndopt\[18\] 2 REG LC_X21_Y10_N1 1 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y10_N1; Fanout = 1; REG Node = 'rndopt\[18\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { en rndopt[18] } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { en rndopt[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { en en~out0 rndopt[18] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.875 ns + Longest register pin " "Info: + Longest register to pin delay is 5.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rndopt\[18\] 1 REG LC_X21_Y10_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y10_N1; Fanout = 1; REG Node = 'rndopt\[18\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rndopt[18] } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.751 ns) + CELL(2.124 ns) 5.875 ns rndop\[17\] 2 PIN PIN_43 0 " "Info: 2: + IC(3.751 ns) + CELL(2.124 ns) = 5.875 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'rndop\[17\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.875 ns" { rndopt[18] rndop[17] } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 36.15 % ) " "Info: Total cell delay = 2.124 ns ( 36.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.751 ns ( 63.85 % ) " "Info: Total interconnect delay = 3.751 ns ( 63.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.875 ns" { rndopt[18] rndop[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.875 ns" { rndopt[18] rndop[17] } { 0.000ns 3.751ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { en rndopt[18] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { en en~out0 rndopt[18] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.875 ns" { rndopt[18] rndop[17] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.875 ns" { rndopt[18] rndop[17] } { 0.000ns 3.751ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "rndopt\[2\] rndip\[1\] en -4.260 ns register " "Info: th for register \"rndopt\[2\]\" (data pin = \"rndip\[1\]\", clock pin = \"en\") is -4.260 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "en destination 2.942 ns + Longest register " "Info: + Longest clock path from clock \"en\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns en 1 CLK PIN_29 28 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 28; CLK Node = 'en'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns rndopt\[2\] 2 REG LC_X21_Y12_N5 1 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y12_N5; Fanout = 1; REG Node = 'rndopt\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { en rndopt[2] } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { en rndopt[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { en en~out0 rndopt[2] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.217 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.217 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rndip\[1\] 1 PIN PIN_28 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 3; PIN Node = 'rndip\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rndip[1] } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.687 ns) + CELL(0.590 ns) 3.746 ns process0~15596 2 COMB LC_X14_Y11_N7 1 " "Info: 2: + IC(1.687 ns) + CELL(0.590 ns) = 3.746 ns; Loc. = LC_X14_Y11_N7; Fanout = 1; COMB Node = 'process0~15596'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.277 ns" { rndip[1] process0~15596 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.443 ns) + CELL(0.292 ns) 4.481 ns process0~15605 3 COMB LC_X14_Y11_N9 3 " "Info: 3: + IC(0.443 ns) + CELL(0.292 ns) = 4.481 ns; Loc. = LC_X14_Y11_N9; Fanout = 3; COMB Node = 'process0~15605'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { process0~15596 process0~15605 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.998 ns) + CELL(0.738 ns) 7.217 ns rndopt\[2\] 4 REG LC_X21_Y12_N5 1 " "Info: 4: + IC(1.998 ns) + CELL(0.738 ns) = 7.217 ns; Loc. = LC_X21_Y12_N5; Fanout = 1; REG Node = 'rndopt\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.736 ns" { process0~15605 rndopt[2] } "NODE_NAME" } } { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.089 ns ( 42.80 % ) " "Info: Total cell delay = 3.089 ns ( 42.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.128 ns ( 57.20 % ) " "Info: Total interconnect delay = 4.128 ns ( 57.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.217 ns" { rndip[1] process0~15596 process0~15605 rndopt[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.217 ns" { rndip[1] rndip[1]~out0 process0~15596 process0~15605 rndopt[2] } { 0.000ns 0.000ns 1.687ns 0.443ns 1.998ns } { 0.000ns 1.469ns 0.590ns 0.292ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { en rndopt[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { en en~out0 rndopt[2] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.217 ns" { rndip[1] process0~15596 process0~15605 rndopt[2] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.217 ns" { rndip[1] rndip[1]~out0 process0~15596 process0~15605 rndopt[2] } { 0.000ns 0.000ns 1.687ns 0.443ns 1.998ns } { 0.000ns 1.469ns 0.590ns 0.292ns 0.738ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 10 21:04:46 2007 " "Info: Processing ended: Tue Apr 10 21:04:46 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}