round.map.qmsg

Simple 32 bit Floating point Multiplier

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 10 21:03:45 2007 " "Info: Processing started: Tue Apr 10 21:03:45 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Round -c Round " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Round -c Round" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Round.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Round.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Round-beh " "Info: Found design unit 1: Round-beh" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 Round " "Info: Found entity 1: Round" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Round " "Info: Elaborating entity \"Round\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "aexpt\[7\] data_in GND " "Warning: Reduced register \"aexpt\[7\]\" with stuck data_in port to stuck value GND" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "aexpt\[6\] data_in GND " "Warning: Reduced register \"aexpt\[6\]\" with stuck data_in port to stuck value GND" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "aexpt\[5\] data_in GND " "Warning: Reduced register \"aexpt\[5\]\" with stuck data_in port to stuck value GND" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 20 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "addexp\[5\] GND " "Warning: Pin \"addexp\[5\]\" stuck at GND" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "addexp\[6\] GND " "Warning: Pin \"addexp\[6\]\" stuck at GND" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "addexp\[7\] GND " "Warning: Pin \"addexp\[7\]\" stuck at GND" {  } { { "Round.vhd" "" { Text "E:/VHDL programs/FPmul/Round/Round.vhd" 9 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "528 " "Info: Implemented 528 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "47 " "Info: Implemented 47 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "31 " "Info: Implemented 31 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "450 " "Info: Implemented 450 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Allocated 152 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 10 21:04:15 2007 " "Info: Processing ended: Tue Apr 10 21:04:15 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:30 " "Info: Elapsed time: 00:00:30" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}