round.vho

Simple 32 bit Floating point Multiplier

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 7.1 Build 156 04/30/2007 SJ Web Edition"

-- DATE "04/10/2007 21:04:50"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	Round IS
    PORT (
	rndip : IN std_logic_vector(45 DOWNTO 0);
	en : IN std_logic;
	rndop : OUT std_logic_vector(22 DOWNTO 0);
	addexp : OUT std_logic_vector(7 DOWNTO 0)
	);
END Round;

ARCHITECTURE structure OF Round IS
SIGNAL GNDs : std_logic_vector(2048 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(2048 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL ww_rndip : std_logic_vector(45 DOWNTO 0);
SIGNAL ww_en : std_logic;
SIGNAL ww_rndop : std_logic_vector(22 DOWNTO 0);
SIGNAL ww_addexp : std_logic_vector(7 DOWNTO 0);
SIGNAL \en~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[37]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[38]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[41]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[39]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[40]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[45]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[42]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[44]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[43]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15543_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15543_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~160_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~160_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[35]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[36]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15544_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15544_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~274_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~274_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[34]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[33]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~332_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~332_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[25]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[24]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[27]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[28]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[26]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[30]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[31]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[29]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[32]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~361_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~361_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~448_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~448_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~538_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~538_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15565_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15565_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[3]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[1]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~568_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~568_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15566_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15566_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[2]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15567_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15567_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[5]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[4]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~478_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~478_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[6]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15568_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15568_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[8]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[10]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~390_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~390_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[9]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[7]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15569_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15569_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15570_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15570_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15571_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15571_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15572_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15572_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15573_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15573_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[23]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~628_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~628_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[0]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15574_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15574_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[11]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[14]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[16]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15583_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15583_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[15]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~216_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~216_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[13]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15584_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15584_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15585_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15585_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15582_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15582_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15586_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15586_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15587_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15587_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[12]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[19]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15577_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15577_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15578_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15578_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[21]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[20]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15579_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15579_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[22]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15580_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15580_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rndip[18]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \rndip[17]~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \process0~15575_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15575_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~104_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~104_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15576_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15576_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15581_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15581_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15588_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15588_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15589_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15589_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15548_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15548_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15550_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15550_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15549_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15549_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15551_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15551_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15552_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15552_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15553_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15553_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15554_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15554_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15555_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15555_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15556_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15556_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15547_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15547_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15557_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15557_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15558_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15558_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15559_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15559_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~508_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~508_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15545_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15545_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~15546_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~15546_pathsel\ : std_logic_vector(10 DOWNTO 0);