displayvalue.vhd

来自「DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计」· VHDL 代码 · 共 42 行

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity displayvalue is
    port (
        clk: in STD_LOGIC;
        d_in: in STD_LOGIC_VECTOR (10 downto 0);
        d_out: out STD_LOGIC_VECTOR (3 downto 0);
        sel: out STD_LOGIC_VECTOR (1 downto 0)
    );
end displayvalue;

architecture displayvalue_arch of displayvalue is
signal temp : std_logic_vector(1 downto 0);
begin
  -- <<enter your statements here>>
process(clk)
begin
if clk='1' and clk'event then
  sel<=temp;
  case temp is 
    when "00" =>
      d_out(3)<='0';
      d_out(2 downto 0)<=d_in(10 downto 8);
    when "01" =>
      d_out<=d_in(7 downto 4);
    when "10" =>
      d_out<=d_in(3 downto 0);
    when others =>
      d_out<="0000";
  end case;
  if temp>=2 then
     temp<="00";
  else
     temp<=temp+1;
  end if;
end if;
end process;
end displayvalue_arch;