wavegenerator.vhd

来自「DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计」· VHDL 代码 · 共 37 行

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity wavegenerator is
    port (
        clk: in STD_LOGIC;
        reset: in STD_LOGIC;
        daout: out STD_LOGIC_VECTOR (7 downto 0)
    );
end wavegenerator;

architecture wavegenerator_arch of wavegenerator is
signal da : std_logic_vector(7 downto 0);
begin
  -- <<enter your statements here>>

  process(clk,reset,da)
  begin
  if reset='0' then
   da<="00000000";
   daout<="00000000";
  else
    if clk='1' and clk'event then
         if da<255 then
            da<=da+1;
         else
            da<="00000000";
         end if;
    end if;
    daout<=da;
  end if;
  end process;

end wavegenerator_arch;