📄 demo7.rpt
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_X003 = EXP( _LC051 & _LC113 & _LC114 & _LC115 & _LC116);
_X002 = EXP( _LC089 & _LC120 & !_LC121 & !_LC123);
_X004 = EXP( _LC089 & _LC113 & _LC114 & _LC115 & _LC116 & _LC120 &
_LC121 & _LC123);
-- Node name is '|SIGNALVALUE:3|:15' = '|SIGNALVALUE:3|da9'
-- Equation name is '_LC122', type is buried
_LC122 = TFFE( _EQ041, GLOBAL( CKSCN), GLOBAL( RESET), VCC, VCC);
_EQ041 = _LC089 & _LC113 & !_LC114 & !_LC115 & _LC116 & !_LC117 &
!_LC120 & _LC121 & _LC122 & !_LC123 & !_LC124
# _LC089 & _LC113 & _LC114 & _LC115 & _LC116 & _LC117 &
_LC120 & _LC121 & _LC123 & _X002
# _LC051 & _LC089 & _LC113 & _LC114 & _LC115 & _LC116 &
_LC117 & _LC120 & !_LC121 & !_LC123
# _LC089 & !_LC113 & _LC114 & !_LC115 & _LC116 & _LC117 &
_LC120 & !_LC121 & !_LC123;
_X002 = EXP( _LC089 & _LC120 & !_LC121 & !_LC123);
-- Node name is '|SIGNALVALUE:3|:14' = '|SIGNALVALUE:3|da10'
-- Equation name is '_LC124', type is buried
_LC124 = TFFE( _EQ042, GLOBAL( CKSCN), GLOBAL( RESET), VCC, VCC);
_EQ042 = _LC089 & _LC113 & _LC114 & _LC115 & _LC116 & _LC117 &
_LC120 & _LC121 & _LC122 & _LC123 & _X002
# _LC051 & _LC089 & _LC113 & _LC114 & _LC115 & _LC116 &
_LC117 & _LC120 & !_LC121 & _LC122 & !_LC123
# _LC089 & !_LC113 & _LC114 & !_LC115 & _LC116 & _LC117 &
_LC120 & !_LC121 & _LC122 & !_LC123;
_X002 = EXP( _LC089 & _LC120 & !_LC121 & !_LC123);
-- Node name is '|SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC051', type is buried
_LC051 = LCELL( _EQ043 $ _LC120);
_EQ043 = !_LC089 & _LC120 & !_LC121 & !_LC123;
-- Node name is '|SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC060', type is buried
_LC060 = LCELL(!_LC120 $ _EQ044);
_EQ044 = !_LC089 & !_LC121 & !_LC123;
-- Node name is '|SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC088', type is buried
_LC088 = LCELL( _LC115 $ _EQ045);
_EQ045 = _LC051 & _LC116;
-- Node name is '|SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC087', type is buried
_LC087 = LCELL( _LC113 $ _EQ046);
_EQ046 = _LC051 & _LC115 & _LC116;
-- Node name is '|SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC086', type is buried
_LC086 = LCELL( _LC114 $ _EQ047);
_EQ047 = _LC051 & _LC113 & _LC115 & _LC116;
-- Node name is '|SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC050', type is buried
_LC050 = LCELL( _LC120 $ _EQ048);
_EQ048 = _LC089 & _LC121 & _LC123;
-- Node name is '|SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC061', type is buried
_LC061 = LCELL( _LC115 $ _EQ049);
_EQ049 = _LC089 & _LC116 & _LC120 & _LC121 & _LC123;
-- Node name is '|SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC059', type is buried
_LC059 = LCELL( _LC113 $ _EQ050);
_EQ050 = _LC089 & _LC115 & _LC116 & _LC120 & _LC121 & _LC123;
-- Node name is '|SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC125', type is buried
_LC125 = LCELL( _LC114 $ _EQ051);
_EQ051 = _LC089 & _LC113 & _LC115 & _LC116 & _LC120 & _LC121 &
_LC123;
-- Node name is '|WAVEGENERATOR:4|:18' = '|WAVEGENERATOR:4|da0'
-- Equation name is '_LC090', type is buried
_LC090 = TFFE( VCC, GLOBAL( CKSCN), GLOBAL( RESET), VCC, VCC);
-- Node name is '|WAVEGENERATOR:4|:17' = '|WAVEGENERATOR:4|da1'
-- Equation name is '_LC058', type is buried
_LC058 = TFFE( _LC090, GLOBAL( CKSCN), GLOBAL( RESET), VCC, VCC);
-- Node name is '|WAVEGENERATOR:4|:16' = '|WAVEGENERATOR:4|da2'
-- Equation name is '_LC049', type is buried
_LC049 = TFFE( _EQ052, GLOBAL( CKSCN), GLOBAL( RESET), VCC, VCC);
_EQ052 = _LC058 & _LC090;
-- Node name is '|WAVEGENERATOR:4|:15' = '|WAVEGENERATOR:4|da3'
-- Equation name is '_LC066', type is buried
_LC066 = DFFE( _EQ053 $ _LC052, GLOBAL( CKSCN), GLOBAL( RESET), VCC, VCC);
_EQ053 = _LC049 & _LC052 & _LC058 & _LC066 & _LC068 & _LC074 &
_LC078 & _LC079 & _LC090;
-- Node name is '|WAVEGENERATOR:4|:14' = '|WAVEGENERATOR:4|da4'
-- Equation name is '_LC074', type is buried
_LC074 = DFFE( _EQ054 $ _LC053, GLOBAL( CKSCN), GLOBAL( RESET), VCC, VCC);
_EQ054 = _LC049 & _LC053 & _LC058 & _LC066 & _LC068 & _LC074 &
_LC078 & _LC079 & _LC090;
-- Node name is '|WAVEGENERATOR:4|:13' = '|WAVEGENERATOR:4|da5'
-- Equation name is '_LC068', type is buried
_LC068 = DFFE( _EQ055 $ _LC070, GLOBAL( CKSCN), GLOBAL( RESET), VCC, VCC);
_EQ055 = _LC049 & _LC058 & _LC066 & _LC068 & _LC070 & _LC074 &
_LC078 & _LC079 & _LC090;
-- Node name is '|WAVEGENERATOR:4|:12' = '|WAVEGENERATOR:4|da6'
-- Equation name is '_LC079', type is buried
_LC079 = DFFE( _EQ056 $ _LC071, GLOBAL( CKSCN), GLOBAL( RESET), VCC, VCC);
_EQ056 = _LC049 & _LC058 & _LC066 & _LC068 & _LC071 & _LC074 &
_LC078 & _LC079 & _LC090;
-- Node name is '|WAVEGENERATOR:4|:11' = '|WAVEGENERATOR:4|da7'
-- Equation name is '_LC078', type is buried
_LC078 = DFFE( _EQ057 $ _LC076, GLOBAL( CKSCN), GLOBAL( RESET), VCC, VCC);
_EQ057 = _LC049 & _LC058 & _LC066 & _LC068 & _LC074 & _LC076 &
_LC078 & _LC079 & _LC090;
-- Node name is '|WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC052', type is buried
_LC052 = LCELL( _LC066 $ _EQ058);
_EQ058 = _LC049 & _LC058 & _LC090;
-- Node name is '|WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC053', type is buried
_LC053 = LCELL( _LC074 $ _EQ059);
_EQ059 = _LC049 & _LC058 & _LC066 & _LC090;
-- Node name is '|WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC070', type is buried
_LC070 = LCELL( _LC068 $ _EQ060);
_EQ060 = _LC049 & _LC058 & _LC066 & _LC074 & _LC090;
-- Node name is '|WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC071', type is buried
_LC071 = LCELL( _LC079 $ _EQ061);
_EQ061 = _LC049 & _LC058 & _LC066 & _LC068 & _LC074 & _LC090;
-- Node name is '|WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC076', type is buried
_LC076 = LCELL( _LC078 $ _EQ062);
_EQ062 = _LC049 & _LC058 & _LC066 & _LC068 & _LC074 & _LC079 &
_LC090;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,994K
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