📄 demo7.rpt
字号:
C: LC33 - LC48 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 14/16( 87%) 8/ 8(100%) 0/16( 0%) 13/36( 36%)
E: LC65 - LC80 16/16(100%) 8/ 8(100%) 0/16( 0%) 14/36( 38%)
F: LC81 - LC96 16/16(100%) 3/ 8( 37%) 0/16( 0%) 20/36( 55%)
G: LC97 - LC112 7/16( 43%) 8/ 8(100%) 0/16( 0%) 4/36( 11%)
H: LC113 - LC128 16/16(100%) 3/ 8( 37%) 8/16( 50%) 21/36( 58%)
Total dedicated input pins used: 3/4 ( 75%)
Total I/O pins used: 32/64 ( 50%)
Total logic cells used: 69/128 ( 53%)
Total shareable expanders used: 4/128 ( 3%)
Total Turbo logic cells used: 69/128 ( 53%)
Total shareable expanders not available (n/a): 4/128 ( 3%)
Average fan-in: 5.78
Total fan-in: 399
Total input pins required: 12
Total fast input logic cells required: 0
Total output pins required: 19
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 69
Total flipflops required: 38
Total product terms required: 161
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 4
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt
demo7
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
74 (117) (H) INPUT 0 0 0 0 0 2 6 CKDSP
83 - - INPUT G 0 0 0 0 0 0 0 CKSCN
2 - - INPUT G 0 0 0 0 0 0 0 JMP
1 - - INPUT G 0 0 0 0 0 8 15 RESET
33 (64) (D) INPUT 0 0 0 0 0 0 0 SW1
34 (61) (D) INPUT 0 0 0 0 0 0 0 SW2
35 (59) (D) INPUT 0 0 0 0 0 0 0 SW3
36 (57) (D) INPUT 0 0 0 0 0 0 0 SW4
37 (56) (D) INPUT 0 0 0 0 0 0 0 SW5
39 (53) (D) INPUT 0 0 0 0 0 0 0 SW6
40 (51) (D) INPUT 0 0 0 0 0 0 0 SW7
41 (49) (D) INPUT 0 0 0 0 0 0 0 SW8
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt
demo7
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
63 97 G OUTPUT t 0 0 0 0 4 0 0 A
64 99 G OUTPUT t 0 0 0 0 4 0 0 B
65 101 G OUTPUT t 0 0 0 0 4 0 0 C
67 104 G OUTPUT t 0 0 0 0 4 0 0 D
44 65 E OUTPUT t 0 0 0 1 1 0 0 DAOUT0
45 67 E OUTPUT t 0 0 0 1 1 0 0 DAOUT1
46 69 E OUTPUT t 0 0 0 1 1 0 0 DAOUT2
48 72 E OUTPUT t 0 0 0 1 1 0 0 DAOUT3
49 73 E OUTPUT t 0 0 0 1 1 0 0 DAOUT4
50 75 E OUTPUT t 0 0 0 1 1 0 0 DAOUT5
51 77 E OUTPUT t 0 0 0 1 1 0 0 DAOUT6
52 80 E OUTPUT t 0 0 0 1 1 0 0 DAOUT7
68 105 G OUTPUT t 0 0 0 0 4 0 0 E
69 107 G OUTPUT t 0 0 0 0 4 0 0 F
70 109 G OUTPUT t 0 0 0 0 4 0 0 G
80 126 H OUTPUT t 0 0 0 0 0 0 0 IO_DS1
81 128 H OUTPUT t 0 0 0 0 0 0 0 IO_DS2
58 91 F FF t 0 0 0 1 1 0 0 SS0
60 93 F FF t 0 0 0 1 1 0 0 SS1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt
demo7
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(75) 118 H DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da10 (|CHECOUTVALUE:1|:25)
- 119 H DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da9 (|CHECOUTVALUE:1|:26)
- 127 H DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da8 (|CHECOUTVALUE:1|:27)
- 92 F DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da7 (|CHECOUTVALUE:1|:28)
- 54 D DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da6 (|CHECOUTVALUE:1|:29)
(61) 94 F DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da5 (|CHECOUTVALUE:1|:30)
- 95 F DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da4 (|CHECOUTVALUE:1|:31)
(36) 57 D DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da3 (|CHECOUTVALUE:1|:32)
(37) 56 D DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da2 (|CHECOUTVALUE:1|:33)
- 55 D DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da1 (|CHECOUTVALUE:1|:34)
(33) 64 D DFFE + t 0 0 0 1 1 0 1 |CHECOUTVALUE:1|da0 (|CHECOUTVALUE:1|:35)
(62) 96 F DFFE t 0 0 0 2 4 7 0 |DISPLAYVALUE:2|:13
- 81 F DFFE t 0 0 0 2 5 7 0 |DISPLAYVALUE:2|:15
- 82 F DFFE t 0 0 0 2 5 7 0 |DISPLAYVALUE:2|:17
- 84 F DFFE t 0 0 0 2 5 7 0 |DISPLAYVALUE:2|:19
(55) 85 F TFFE t 0 0 0 1 2 1 6 |DISPLAYVALUE:2|temp1 (|DISPLAYVALUE:2|:25)
(54) 83 F DFFE t 0 0 0 1 2 1 6 |DISPLAYVALUE:2|temp0 (|DISPLAYVALUE:2|:26)
(40) 51 D SOFT t 0 0 0 0 4 0 7 |SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|g4
- 60 D SOFT t 0 0 0 0 4 0 1 |SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|result_node3
(57) 88 F SOFT t 0 0 0 0 3 0 1 |SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|result_node5
- 87 F SOFT t 0 0 0 0 4 0 1 |SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|result_node6
(56) 86 F SOFT t 0 0 0 0 5 0 1 |SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|result_node7
- 50 D SOFT t 0 0 0 0 4 0 1 |SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node3
(34) 61 D SOFT t 0 0 0 0 6 0 1 |SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node5
(35) 59 D SOFT t 0 0 0 0 7 0 1 |SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node6
(79) 125 H SOFT t 0 0 0 0 8 0 1 |SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node7
- 124 H TFFE + t 1 1 0 0 11 0 9 |SIGNALVALUE:3|da10 (|SIGNALVALUE:3|:14)
- 122 H TFFE + t 1 1 0 0 12 0 10 |SIGNALVALUE:3|da9 (|SIGNALVALUE:3|:15)
(74) 117 H TFFE + t 4 2 0 0 9 0 10 |SIGNALVALUE:3|da8 (|SIGNALVALUE:3|:16)
- 114 H DFFE + t 2 1 1 0 13 0 13 |SIGNALVALUE:3|da7 (|SIGNALVALUE:3|:17)
- 113 H DFFE + t 2 1 1 0 13 0 15 |SIGNALVALUE:3|da6 (|SIGNALVALUE:3|:18)
(73) 115 H DFFE + t 2 1 1 0 13 0 17 |SIGNALVALUE:3|da5 (|SIGNALVALUE:3|:19)
- 116 H TFFE + t 1 1 0 0 12 0 17 |SIGNALVALUE:3|da4 (|SIGNALVALUE:3|:20)
(76) 120 H DFFE + t 2 1 1 0 13 0 17 |SIGNALVALUE:3|da3 (|SIGNALVALUE:3|:21)
- 121 H TFFE + t 0 0 0 0 11 0 17 |SIGNALVALUE:3|da2 (|SIGNALVALUE:3|:22)
(77) 123 H TFFE + t 0 0 0 0 11 0 17 |SIGNALVALUE:3|da1 (|SIGNALVALUE:3|:23)
- 89 F TFFE + t 0 0 0 0 0 0 17 |SIGNALVALUE:3|da0 (|SIGNALVALUE:3|:24)
- 52 D SOFT t 0 0 0 0 4 0 1 |WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node3
(39) 53 D SOFT t 0 0 0 0 5 0 1 |WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node4
- 70 E SOFT t 0 0 0 0 6 0 1 |WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node5
- 71 E SOFT t 0 0 0 0 7 0 1 |WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node6
- 76 E SOFT t 0 0 0 0 8 0 1 |WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node7
- 78 E DFFE + t 0 0 0 0 9 1 6 |WAVEGENERATOR:4|da7 (|WAVEGENERATOR:4|:11)
- 79 E DFFE + t 0 0 0 0 9 1 7 |WAVEGENERATOR:4|da6 (|WAVEGENERATOR:4|:12)
- 68 E DFFE + t 0 0 0 0 9 1 8 |WAVEGENERATOR:4|da5 (|WAVEGENERATOR:4|:13)
- 74 E DFFE + t 0 0 0 0 9 1 9 |WAVEGENERATOR:4|da4 (|WAVEGENERATOR:4|:14)
- 66 E DFFE + t 0 0 0 0 9 1 10 |WAVEGENERATOR:4|da3 (|WAVEGENERATOR:4|:15)
(41) 49 D TFFE + t 0 0 0 0 2 1 10 |WAVEGENERATOR:4|da2 (|WAVEGENERATOR:4|:16)
- 58 D TFFE + t 0 0 0 0 1 1 11 |WAVEGENERATOR:4|da1 (|WAVEGENERATOR:4|:17)
- 90 F TFFE + t 0 0 0 0 0 1 12 |WAVEGENERATOR:4|da0 (|WAVEGENERATOR:4|:18)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt
demo7
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+--------------------------- LC54 |CHECOUTVALUE:1|da6
| +------------------------- LC57 |CHECOUTVALUE:1|da3
| | +----------------------- LC56 |CHECOUTVALUE:1|da2
| | | +--------------------- LC55 |CHECOUTVALUE:1|da1
| | | | +------------------- LC64 |CHECOUTVALUE:1|da0
| | | | | +----------------- LC51 |SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|g4
| | | | | | +--------------- LC60 |SIGNALVALUE:3|LPM_ADD_SUB:437|addcore:adder|addcore:adder0|result_node3
| | | | | | | +------------- LC50 |SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node3
| | | | | | | | +----------- LC61 |SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | +--------- LC59 |SIGNALVALUE:3|LPM_ADD_SUB:612|addcore:adder|addcore:adder0|result_node6
| | | | | | | | | | +------- LC52 |WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node3
| | | | | | | | | | | +----- LC53 |WAVEGENERATOR:4|LPM_ADD_SUB:181|addcore:adder|result_node4
| | | | | | | | | | | | +--- LC49 |WAVEGENERATOR:4|da2
| | | | | | | | | | | | | +- LC58 |WAVEGENERATOR:4|da1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':
LC49 -> - - - - - - - - - - * * * - | - - - * * - - - | <-- |WAVEGENERATOR:4|da2
LC58 -> - - - - - - - - - - * * * * | - - - * * - - - | <-- |WAVEGENERATOR:4|da1
Pin
83 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- CKSCN
2 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- JMP
1 -> * * * * * - - - - - - - - - | - - - * * * - * | <-- RESET
LC113-> * - - - - - - - - * - - - - | - - - * - * - * | <-- |SIGNALVALUE:3|da6
LC115-> - - - - - - - - * * - - - - | - - - * - * - * | <-- |SIGNALVALUE:3|da5
LC116-> - - - - - - - - * * - - - - | - - - * - * - * | <-- |SIGNALVALUE:3|da4
LC120-> - * - - - * * * * * - - - - | - - - * - - - * | <-- |SIGNALVALUE:3|da3
LC121-> - - * - - * * * * * - - - - | - - - * - - - * | <-- |SIGNALVALUE:3|da2
LC123-> - - - * - * * * * * - - - - | - - - * - - - * | <-- |SIGNALVALUE:3|da1
LC89 -> - - - - * * * * * * - - - - | - - - * - - - * | <-- |SIGNALVALUE:3|da0
LC74 -> - - - - - - - - - - - * - - | - - - * * - - - | <-- |WAVEGENERATOR:4|da4
LC66 -> - - - - - - - - - - * * - - | - - - * * - - - | <-- |WAVEGENERATOR:4|da3
LC90 -> - - - - - - - - - - * * * * | - - - * * - - - | <-- |WAVEGENERATOR:4|da0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt
demo7
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------------------------------- LC65 DAOUT0
| +----------------------------- LC67 DAOUT1
| | +--------------------------- LC69 DAOUT2
| | | +------------------------- LC72 DAOUT3
| | | | +----------------------- LC73 DAOUT4
| | | | | +--------------------- LC75 DAOUT5
| | | | | | +------------------- LC77 DAOUT6
| | | | | | | +----------------- LC80 DAOUT7
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