demo7.rpt

DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计

Project Information            d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt

MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/15/2004 09:25:14

Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

demo7     EPM7128SLC84-15  12       19       0      69      4           53 %

User Pins:                 12       19       0  



Project Information            d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt

** PROJECT COMPILATION MESSAGES **

Warning: GLOBAL primitive on node 'RESET' feeds logic -- non-global signal usage may result
Warning: Primitive 'IO_DS1' is stuck at GND
Warning: Primitive 'IO_DS2' is stuck at GND
Info: Reserved unused input pin 'SW2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW6' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW8' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board


Project Information            d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'CKSCN' chosen for auto global Clock
INFO: Signal 'JMP' chosen for auto global Clock
INFO: Signal 'RESET' chosen for auto global Clear


Project Information            d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

demo7@63                          A
demo7@64                          B
demo7@65                          C
demo7@74                          CKDSP
demo7@83                          CKSCN
demo7@67                          D
demo7@44                          DAOUT0
demo7@45                          DAOUT1
demo7@46                          DAOUT2
demo7@48                          DAOUT3
demo7@49                          DAOUT4
demo7@50                          DAOUT5
demo7@51                          DAOUT6
demo7@52                          DAOUT7
demo7@68                          E
demo7@69                          F
demo7@70                          G
demo7@80                          IO_DS1
demo7@81                          IO_DS2
demo7@2                           JMP
demo7@1                           RESET
demo7@58                          SS0
demo7@60                          SS1
demo7@33                          SW1
demo7@34                          SW2
demo7@35                          SW3
demo7@36                          SW4
demo7@37                          SW5
demo7@39                          SW6
demo7@40                          SW7
demo7@41                          SW8


Project Information            d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt

** FILE HIERARCHY **



|checoutvalue:1|
|displayvalue:2|
|displayvalue:2|lpm_add_sub:303|
|displayvalue:2|lpm_add_sub:303|addcore:adder|
|displayvalue:2|lpm_add_sub:303|addcore:adder|addcore:adder0|
|displayvalue:2|lpm_add_sub:303|altshift:result_ext_latency_ffs|
|displayvalue:2|lpm_add_sub:303|altshift:carry_ext_latency_ffs|
|displayvalue:2|lpm_add_sub:303|altshift:oflow_ext_latency_ffs|
|signalvalue:3|
|signalvalue:3|lpm_add_sub:356|
|signalvalue:3|lpm_add_sub:356|addcore:adder|
|signalvalue:3|lpm_add_sub:356|addcore:adder|addcore:adder0|
|signalvalue:3|lpm_add_sub:356|altshift:result_ext_latency_ffs|
|signalvalue:3|lpm_add_sub:356|altshift:carry_ext_latency_ffs|
|signalvalue:3|lpm_add_sub:356|altshift:oflow_ext_latency_ffs|
|signalvalue:3|lpm_add_sub:437|
|signalvalue:3|lpm_add_sub:437|addcore:adder|
|signalvalue:3|lpm_add_sub:437|addcore:adder|addcore:adder1|
|signalvalue:3|lpm_add_sub:437|addcore:adder|addcore:adder0|
|signalvalue:3|lpm_add_sub:437|altshift:result_ext_latency_ffs|
|signalvalue:3|lpm_add_sub:437|altshift:carry_ext_latency_ffs|
|signalvalue:3|lpm_add_sub:437|altshift:oflow_ext_latency_ffs|
|signalvalue:3|lpm_add_sub:612|
|signalvalue:3|lpm_add_sub:612|addcore:adder|
|signalvalue:3|lpm_add_sub:612|addcore:adder|addcore:adder1|
|signalvalue:3|lpm_add_sub:612|addcore:adder|addcore:adder0|
|signalvalue:3|lpm_add_sub:612|altshift:result_ext_latency_ffs|
|signalvalue:3|lpm_add_sub:612|altshift:carry_ext_latency_ffs|
|signalvalue:3|lpm_add_sub:612|altshift:oflow_ext_latency_ffs|
|wavegenerator:4|
|wavegenerator:4|lpm_add_sub:181|
|wavegenerator:4|lpm_add_sub:181|addcore:adder|
|wavegenerator:4|lpm_add_sub:181|altshift:result_ext_latency_ffs|
|wavegenerator:4|lpm_add_sub:181|altshift:carry_ext_latency_ffs|
|wavegenerator:4|lpm_add_sub:181|altshift:oflow_ext_latency_ffs|
|xdeled:5|
|74244:19|


Device-Specific Information:   d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt
demo7

***** Logic for device 'demo7' compiled without errors.




Device: EPM7128SLC84-15

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    Enable JTAG Support                        = ON
    User Code                                  = ffff
    MultiVolt I/O                              = OFF

              R  R  R  R     R  R  R                          R     R  R  R  
              E  E  E  E     E  E  E                          E     E  E  E  
              S  S  S  S     S  S  S  V                 I  I  S     S  S  S  
              E  E  E  E     E  E  E  C     R     C     O  O  E  V  E  E  E  
              R  R  R  R     R  R  R  C     E     K     _  _  R  C  R  R  R  
              V  V  V  V  G  V  V  V  I  J  S  G  S  G  D  D  V  C  V  V  V  
              E  E  E  E  N  E  E  E  N  M  E  N  C  N  S  S  E  I  E  E  E  
              D  D  D  D  D  D  D  D  T  P  T  D  N  D  2  1  D  O  D  D  D  
            -----------------------------------------------------------------_ 
          /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
RESERVED | 12                                                              74 | CKDSP 
   VCCIO | 13                                                              73 | RESERVED 
    #TDI | 14                                                              72 | GND 
RESERVED | 15                                                              71 | #TDO 
RESERVED | 16                                                              70 | G 
RESERVED | 17                                                              69 | F 
RESERVED | 18                                                              68 | E 
     GND | 19                                                              67 | D 
RESERVED | 20                                                              66 | VCCIO 
RESERVED | 21                                                              65 | C 
RESERVED | 22                       EPM7128SLC84-15                        64 | B 
    #TMS | 23                                                              63 | A 
RESERVED | 24                                                              62 | #TCK 
RESERVED | 25                                                              61 | RESERVED 
   VCCIO | 26                                                              60 | SS1 
RESERVED | 27                                                              59 | GND 
RESERVED | 28                                                              58 | SS0 
RESERVED | 29                                                              57 | RESERVED 
RESERVED | 30                                                              56 | RESERVED 
RESERVED | 31                                                              55 | RESERVED 
     GND | 32                                                              54 | RESERVED 
         |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
           ------------------------------------------------------------------ 
              S  S  S  S  S  V  S  S  S  G  V  D  D  D  G  D  D  D  D  D  V  
              W  W  W  W  W  C  W  W  W  N  C  A  A  A  N  A  A  A  A  A  C  
              1  2  3  4  5  C  6  7  8  D  C  O  O  O  D  O  O  O  O  O  C  
                             I              I  U  U  U     U  U  U  U  U  I  
                             O              N  T  T  T     T  T  T  T  T  O  
                                            T  0  1  2     3  4  5  6  7     
                                                                             
                                                                             


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:   d:\eda-240h\altera\7128_84_vhdl\demo7\demo7.rpt
demo7

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   0/ 8(  0%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32     0/16(  0%)   1/ 8( 12%)   0/16(  0%)   0/36(  0%)