signalvalue.vhd

来自「DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计」· VHDL 代码 · 共 44 行

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity signalvalue is
    port (
        clk: in STD_LOGIC;
        reset: in STD_LOGIC;
        daout: out STD_LOGIC_VECTOR (10 downto 0)
    );
end signalvalue;

architecture signalvalue_arch of signalvalue is
signal da : std_logic_vector(10 downto 0);
begin
  -- <<enter your statements here>>
process(clk,reset,da)
begin
if reset='0' then
   da<="00000000000";
   daout<="00000000000";
else
   if clk='1' and clk'event then
     if da(3 downto 0)=9 then
        if da(7 downto 4)=9 then
           da(7 downto 0)<="00000000";
           da(10 downto 8)<=da(10 downto 8)+1;
        else
           da<=da+7;
        end if;
     else
        if da/="01001010101" then
             da<=da+1;
        else
             da<="00000000000";
        end if;
     end if;
   end if;
   daout<=da;
end if;
end process;
end signalvalue_arch;