checoutvalue.vhd

DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity checoutvalue is
    port (
        reset: in STD_LOGIC;
        jmp: in STD_LOGIC;
        d_in: in STD_LOGIC_VECTOR (10 downto 0);
        d_out: out STD_LOGIC_VECTOR (10 downto 0)
    );
end checoutvalue;

architecture checoutvalue_arch of checoutvalue is
signal da : std_logic_vector(10 downto 0);
begin
  -- <<enter your statements here>>

process(reset,da)
begin
case reset is
 when '0' =>
   d_out<="00000000000";
 when others =>
   d_out<=da;
end case;
end process;

process(jmp)
begin
   if jmp='1' and jmp'event then
    da<=d_in;
   end if;
end process;

end checoutvalue_arch;