wavegenerator.vhd

DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity wavegenerator is
    port (
        clk: in STD_LOGIC;
        reset: in STD_LOGIC;
        mode: in STD_LOGIC_VECTOR (1 downto 0);
        d_out: out STD_LOGIC_VECTOR (7 downto 0)
    );
end wavegenerator;

architecture wavegenerator_arch of wavegenerator is
signal da : std_logic_vector(7 downto 0);
begin
  -- <<enter your statements here>>
  process(clk,reset,mode,da)
  variable porn : std_logic;
  begin
  if reset='0' then
   da<="00000000";
   d_out<="00000000";
   porn:='0';
  else
    if clk='1' and clk'event then
      case mode is
       when "00" =>
         if da<255 then
            da<=da+1;
         else
            da<="00000000";
         end if;
       when "01" =>
         if da=0 then
            da<="11111111";
         else
            da<=da-1;
         end if;
       when "10" =>
         if porn='0' then
          if da<255 then
             da<=da+1;
          else
             porn:='1';
          end if;
         else
          if da>0 then
             da<=da-1;
          else
             porn:='0';
          end if;
         end if;
       when "11" =>
        if da<240 then
           da<=da+32;
        else
           da<="00000000";
        end if;
       when others =>
        da<="00000000";
      end case; 
    end if;
    d_out<=da;
  end if;
  end process;

end wavegenerator_arch;