📄 demo6.rpt
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-- Equation name is '_LC114', type is buried
-- synthesized logic cell
_LC114 = LCELL( _EQ043 $ GND);
_EQ043 = !_LC082 & _LC091 & MODE0 & MODE1
# _LC091 & !_LC121 & MODE0 & MODE1
# !_LC076 & _LC124 & !MODE0 & MODE1
# _LC066 & !_LC106 & !MODE0 & !MODE1
# !_LC051 & _LC066 & !MODE0 & !MODE1;
-- Node name is '|WAVEGENERATOR:11|~1086~1'
-- Equation name is '_LC097', type is buried
-- synthesized logic cell
_LC097 = LCELL( _EQ044 $ GND);
_EQ044 = _LC076 & _LC106 & _LC123 & !MODE0 & MODE1
# _LC051 & _LC076 & _LC123 & !MODE0 & MODE1
# _LC076 & _LC081 & _LC123 & !MODE0 & MODE1
# _LC074 & _LC076 & _LC123 & !MODE0 & MODE1
# _LC050 & _LC076 & _LC123 & !MODE0 & MODE1;
-- Node name is '|WAVEGENERATOR:11|~1086~2'
-- Equation name is '_LC098', type is buried
-- synthesized logic cell
_LC098 = LCELL( _EQ045 $ GND);
_EQ045 = _LC071 & _LC076 & _LC123 & !MODE0 & MODE1
# _LC076 & _LC082 & _LC123 & !MODE0 & MODE1
# _LC076 & _LC121 & _LC123 & !MODE0 & MODE1
# _LC084 & !_LC106 & MODE0 & MODE1
# !_LC051 & _LC084 & MODE0 & MODE1;
-- Node name is '|WAVEGENERATOR:11|~1086~3'
-- Equation name is '_LC102', type is buried
-- synthesized logic cell
_LC102 = LCELL( _EQ046 $ GND);
_EQ046 = !_LC082 & _LC084 & MODE0 & MODE1
# _LC084 & !_LC121 & MODE0 & MODE1
# !_LC076 & _LC125 & !MODE0 & MODE1
# !_LC106 & _LC116 & !MODE0 & !MODE1
# !_LC051 & _LC116 & !MODE0 & !MODE1;
-- Node name is '|WAVEGENERATOR:11|~1098~1'
-- Equation name is '_LC105', type is buried
-- synthesized logic cell
_LC105 = LCELL( _EQ047 $ GND);
_EQ047 = _LC076 & _LC106 & _LC110 & !MODE0 & MODE1
# _LC051 & _LC076 & _LC110 & !MODE0 & MODE1
# _LC076 & _LC081 & _LC110 & !MODE0 & MODE1
# _LC074 & _LC076 & _LC110 & !MODE0 & MODE1
# _LC050 & _LC076 & _LC110 & !MODE0 & MODE1;
-- Node name is '|WAVEGENERATOR:11|~1098~2'
-- Equation name is '_LC107', type is buried
-- synthesized logic cell
_LC107 = LCELL( _EQ048 $ GND);
_EQ048 = _LC071 & _LC076 & _LC110 & !MODE0 & MODE1
# _LC076 & _LC082 & _LC110 & !MODE0 & MODE1
# _LC076 & _LC110 & _LC121 & !MODE0 & MODE1
# !_LC082 & !_LC106 & MODE0 & MODE1
# !_LC051 & !_LC082 & MODE0 & MODE1;
-- Node name is '|WAVEGENERATOR:11|~1098~3'
-- Equation name is '_LC089', type is buried
-- synthesized logic cell
_LC089 = LCELL( _EQ049 $ GND);
_EQ049 = !_LC082 & MODE0 & MODE1
# !_LC082 & !_LC121 & MODE0 & MODE1
# !_LC076 & _LC118 & !MODE0 & MODE1
# !_LC106 & _LC117 & !MODE0 & !MODE1
# !_LC051 & _LC117 & !MODE0 & !MODE1;
-- Node name is '|WAVEGENERATOR:11|~1110~1'
-- Equation name is '_LC057', type is buried
-- synthesized logic cell
_LC057 = LCELL( _EQ050 $ GND);
_EQ050 = _LC076 & _LC101 & _LC106 & !MODE0 & MODE1
# _LC051 & _LC076 & _LC101 & !MODE0 & MODE1
# _LC076 & _LC081 & _LC101 & !MODE0 & MODE1
# _LC074 & _LC076 & _LC101 & !MODE0 & MODE1
# _LC050 & _LC076 & _LC101 & !MODE0 & MODE1;
-- Node name is '|WAVEGENERATOR:11|~1110~2'
-- Equation name is '_LC061', type is buried
-- synthesized logic cell
_LC061 = LCELL( _EQ051 $ GND);
_EQ051 = _LC071 & _LC076 & _LC101 & !MODE0 & MODE1
# _LC076 & _LC082 & _LC101 & !MODE0 & MODE1
# _LC076 & _LC101 & _LC121 & !MODE0 & MODE1
# _LC051 & !_LC106 & MODE0 & MODE1
# _LC051 & !_LC082 & MODE0 & MODE1;
-- Node name is '|WAVEGENERATOR:11|~1110~3'
-- Equation name is '_LC054', type is buried
-- synthesized logic cell
_LC054 = LCELL( _EQ052 $ GND);
_EQ052 = _LC051 & !_LC121 & MODE0 & MODE1
# !_LC076 & _LC109 & !MODE0 & MODE1
# _LC104 & !_LC106 & !MODE0 & !MODE1
# !_LC051 & _LC104 & !MODE0 & !MODE1
# !_LC081 & _LC104 & !MODE0 & !MODE1;
-- Node name is '|WAVEGENERATOR:11|~1122~1'
-- Equation name is '_LC052', type is buried
-- synthesized logic cell
_LC052 = LCELL( _EQ053 $ GND);
_EQ053 = _LC076 & _LC103 & _LC106 & !MODE0 & MODE1
# _LC051 & _LC076 & _LC103 & !MODE0 & MODE1
# _LC076 & _LC081 & _LC103 & !MODE0 & MODE1
# _LC074 & _LC076 & _LC103 & !MODE0 & MODE1
# _LC050 & _LC076 & _LC103 & !MODE0 & MODE1;
-- Node name is '|WAVEGENERATOR:11|~1122~2'
-- Equation name is '_LC049', type is buried
-- synthesized logic cell
_LC049 = LCELL( _EQ054 $ GND);
_EQ054 = _LC071 & _LC076 & _LC103 & !MODE0 & MODE1
# _LC076 & _LC082 & _LC103 & !MODE0 & MODE1
# _LC076 & _LC103 & _LC121 & !MODE0 & MODE1
# _LC071 & !_LC106 & MODE0 & MODE1
# !_LC051 & _LC071 & MODE0 & MODE1;
-- Node name is '|WAVEGENERATOR:11|~1122~3'
-- Equation name is '_LC078', type is buried
-- synthesized logic cell
_LC078 = LCELL( _EQ055 $ GND);
_EQ055 = _LC071 & !_LC082 & MODE0 & MODE1
# _LC071 & !_LC121 & MODE0 & MODE1
# !_LC076 & _LC112 & !MODE0 & MODE1
# !_LC106 & _LC108 & !MODE0 & !MODE1
# !_LC051 & _LC108 & !MODE0 & !MODE1;
-- Node name is '|WAVEGENERATOR:11|~1122~4'
-- Equation name is '_LC070', type is buried
-- synthesized logic cell
_LC070 = LCELL( _EQ056 $ GND);
_EQ056 = !_LC081 & _LC108 & !MODE0 & !MODE1
# !_LC074 & _LC108 & !MODE0 & !MODE1
# !_LC050 & _LC108 & !MODE0 & !MODE1
# !_LC071 & _LC108 & !MODE0 & !MODE1
# !_LC082 & _LC108 & !MODE0 & !MODE1;
-- Node name is '|WAVEGENERATOR:11|~1134~1'
-- Equation name is '_LC068', type is buried
-- synthesized logic cell
_LC068 = LCELL( _EQ057 $ GND);
_EQ057 = !_LC050 & !_LC051 & !_LC071 & !_LC081 & !_LC082 & !_LC106 &
!_LC121 & !MODE0
# _LC051 & _LC082 & _LC106 & _LC121 & MODE0 & MODE1
# _LC074 & _LC076 & !_LC081 & MODE1
# !_LC074 & !_LC076 & !_LC081 & MODE1
# !_LC074 & !_LC081 & !MODE0 & !MODE1;
-- Node name is '|WAVEGENERATOR:11|~1146~1'
-- Equation name is '_LC079', type is buried
-- synthesized logic cell
_LC079 = LCELL( _EQ058 $ GND);
_EQ058 = _LC050 & !_LC074 & _LC076 & !MODE0 & MODE1
# _LC050 & _LC074 & !_LC076 & !_LC121 & !MODE0
# _LC050 & _LC074 & !_LC076 & !_LC082 & !MODE0
# _LC050 & !_LC051 & _LC074 & !_LC076 & !MODE0
# _LC050 & _LC074 & !_LC076 & !_LC106 & !MODE0;
-- Node name is '|WAVEGENERATOR:11|~1146~2'
-- Equation name is '_LC111', type is buried
-- synthesized logic cell
_LC111 = LCELL( _EQ059 $ GND);
_EQ059 = !_LC050 & _LC074 & _LC076 & MODE1
# _LC050 & _LC074 & !MODE0 & !MODE1
# _LC050 & !_LC074 & MODE0 & !MODE1
# !_LC050 & !_LC074 & !_LC076 & MODE1
# !_LC050 & !_LC074 & !MODE0 & !MODE1;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X009 occurs in LABs D, E, F, G, H
-- _X010 occurs in LABs D, E, F, G, H
Project Information d:\eda-240h\altera\7128_84_vhdl\demo6\demo6.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile ⌨️ 快捷键说明
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