📄 demo5.rpt
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** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------- LC8 LED0
| +----- LC6 LED1
| | +--- LC5 LED2
| | | +- LC3 LED3
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'A'
LC | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
83 -> - - - - | - - - - - - - - | <-- CLK
1 -> - - - - | - - - - - - - - | <-- RESET
63 -> * - - - | * - - - - - - * | <-- RL0
64 -> - * - - | * - - - - - - * | <-- RL1
65 -> - - * - | * - - - - - - * | <-- RL2
67 -> - - - * | * - * - - - - - | <-- RL3
LC91 -> * * * * | * * * - - - - * | <-- KB0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:d:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
demo5
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------- LC29 LED4
| +----- LC27 LED5
| | +--- LC25 LED6
| | | +- LC24 LED7
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'B'
LC | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
83 -> - - - - | - - - - - - - - | <-- CLK
1 -> - - - - | - - - - - - - - | <-- RESET
68 -> * - - - | - * - - - - - - | <-- RL4
69 -> - * - - | - * - - - - - - | <-- RL5
70 -> - - * - | - * - - - - - - | <-- RL6
73 -> - - - * | - * - - - - - - | <-- RL7
LC91 -> * * * * | * * * - - - - * | <-- KB0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:d:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
demo5
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+- LC35 SPK
|
| Other LABs fed by signals
| that feed LAB 'C'
LC | | A B C D E F G H | Logic cells that feed LAB 'C':
Pin
83 -> - | - - - - - - - - | <-- CLK
1 -> - | - - - - - - - - | <-- RESET
67 -> * | * - * - - - - - | <-- RL3
LC91 -> * | * * * - - - - * | <-- KB0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:d:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
demo5
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+- LC91 KB0
|
| Other LABs fed by signals
| that feed LAB 'F'
LC | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
83 -> - | - - - - - - - - | <-- CLK
1 -> - | - - - - - - - - | <-- RESET
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:d:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
demo5
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----- LC117 GL
| +--- LC118 RL
| | +- LC120 YL
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'H'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'H':
Pin
83 -> - - - | - - - - - - - - | <-- CLK
1 -> - - - | - - - - - - - - | <-- RESET
63 -> - * - | * - - - - - - * | <-- RL0
64 -> * - - | * - - - - - - * | <-- RL1
65 -> - - * | * - - - - - - * | <-- RL2
LC91 -> * * * | * * * - - - - * | <-- KB0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information:d:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
demo5
** EQUATIONS **
CLK : INPUT;
RESET : INPUT;
RL0 : INPUT;
RL1 : INPUT;
RL2 : INPUT;
RL3 : INPUT;
RL4 : INPUT;
RL5 : INPUT;
RL6 : INPUT;
RL7 : INPUT;
SW1 : INPUT;
SW2 : INPUT;
SW3 : INPUT;
SW4 : INPUT;
SW5 : INPUT;
SW6 : INPUT;
SW7 : INPUT;
SW8 : INPUT;
-- Node name is 'GL'
-- Equation name is 'GL', location is LC117, type is output.
GL = LCELL( _EQ001 $ GND);
_EQ001 = KB0 & !RL1;
-- Node name is 'KB0' = ':1'
-- Equation name is 'KB0', type is output
KB0 = TFFE( VCC, GLOBAL( CLK), GLOBAL( RESET), VCC, VCC);
-- Node name is 'LED0'
-- Equation name is 'LED0', location is LC008, type is output.
LED0 = LCELL( _EQ002 $ GND);
_EQ002 = !KB0 & !RL0;
-- Node name is 'LED1'
-- Equation name is 'LED1', location is LC006, type is output.
LED1 = LCELL( _EQ003 $ GND);
_EQ003 = !KB0 & !RL1;
-- Node name is 'LED2'
-- Equation name is 'LED2', location is LC005, type is output.
LED2 = LCELL( _EQ004 $ GND);
_EQ004 = !KB0 & !RL2;
-- Node name is 'LED3'
-- Equation name is 'LED3', location is LC003, type is output.
LED3 = LCELL( _EQ005 $ GND);
_EQ005 = !KB0 & !RL3;
-- Node name is 'LED4'
-- Equation name is 'LED4', location is LC029, type is output.
LED4 = LCELL( _EQ006 $ GND);
_EQ006 = !KB0 & !RL4;
-- Node name is 'LED5'
-- Equation name is 'LED5', location is LC027, type is output.
LED5 = LCELL( _EQ007 $ GND);
_EQ007 = !KB0 & !RL5;
-- Node name is 'LED6'
-- Equation name is 'LED6', location is LC025, type is output.
LED6 = LCELL( _EQ008 $ GND);
_EQ008 = !KB0 & !RL6;
-- Node name is 'LED7'
-- Equation name is 'LED7', location is LC024, type is output.
LED7 = LCELL( _EQ009 $ GND);
_EQ009 = !KB0 & !RL7;
-- Node name is 'RL'
-- Equation name is 'RL', location is LC118, type is output.
RL = LCELL( _EQ010 $ GND);
_EQ010 = KB0 & !RL0;
-- Node name is 'SPK'
-- Equation name is 'SPK', location is LC035, type is output.
SPK = LCELL( _EQ011 $ GND);
_EQ011 = KB0 & !RL3;
-- Node name is 'YL'
-- Equation name is 'YL', location is LC120, type is output.
YL = LCELL( _EQ012 $ GND);
_EQ012 = KB0 & !RL2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Informationd:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
ADT PALACE Compilation = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,858K
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