📄 demo5.rpt
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Project Informationd:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/07/2003 09:37:48
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
demo5 EPM7128SLC84-15 18 13 0 13 0 10 %
User Pins: 18 13 0
Project Informationd:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
** PROJECT COMPILATION MESSAGES **
Info: Reserved unused input pin 'SW5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW6' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW8' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Informationd:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLK' chosen for auto global Clock
INFO: Signal 'RESET' chosen for auto global Clear
Project Informationd:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
demo5@83 CLK
demo5@74 GL
demo5@58 KB0
demo5@9 LED0
demo5@10 LED1
demo5@11 LED2
demo5@12 LED3
demo5@15 LED4
demo5@16 LED5
demo5@17 LED6
demo5@18 LED7
demo5@1 RESET
demo5@75 RL
demo5@63 RL0
demo5@64 RL1
demo5@65 RL2
demo5@67 RL3
demo5@68 RL4
demo5@69 RL5
demo5@70 RL6
demo5@73 RL7
demo5@31 SPK
demo5@33 SW1
demo5@34 SW2
demo5@35 SW3
demo5@36 SW4
demo5@37 SW5
demo5@39 SW6
demo5@40 SW7
demo5@41 SW8
demo5@76 YL
Project Informationd:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
** FILE HIERARCHY **
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|7404:57|
|7404:56|
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|7404:53|
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|7404:49|
|74244:61|
Device-Specific Information:d:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
demo5
***** Logic for device 'demo5' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R
E E E E E E E E
S S S S V S S S S
E E E E C R E E E V E
L L L R R R R C E R R R C R
E E E V G V V V I G S G C G V V V C V
D D D E N E E E N N E N L N E E E I E Y R
2 1 0 D D D D D T D T D K D D D D O D L L
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
LED3 | 12 74 | GL
VCCIO | 13 73 | RL7
#TDI | 14 72 | GND
LED4 | 15 71 | #TDO
LED5 | 16 70 | RL6
LED6 | 17 69 | RL5
LED7 | 18 68 | RL4
GND | 19 67 | RL3
RESERVED | 20 66 | VCCIO
RESERVED | 21 65 | RL2
RESERVED | 22 EPM7128SLC84-15 64 | RL1
#TMS | 23 63 | RL0
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
RESERVED | 27 59 | GND
RESERVED | 28 58 | KB0
RESERVED | 29 57 | RESERVED
RESERVED | 30 56 | RESERVED
SPK | 31 55 | RESERVED
GND | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
S S S S S V S S S G V R R R G R R R R R V
W W W W W C W W W N C E E E N E E E E E C
1 2 3 4 5 C 6 7 8 D C S S S D S S S S S C
I I E E E E E E E E I
O N R R R R R R R R O
T V V V V V V V V
E E E E E E E E
D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information:d:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
demo5
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 4/16( 25%) 4/ 8( 50%) 0/16( 0%) 5/36( 13%)
B: LC17 - LC32 4/16( 25%) 5/ 8( 62%) 0/16( 0%) 5/36( 13%)
C: LC33 - LC48 1/16( 6%) 2/ 8( 25%) 0/16( 0%) 2/36( 5%)
D: LC49 - LC64 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 1/16( 6%) 2/ 8( 25%) 0/16( 0%) 0/36( 0%)
G: LC97 - LC112 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
H: LC113 - LC128 3/16( 18%) 4/ 8( 50%) 0/16( 0%) 4/36( 11%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 33/64 ( 51%)
Total logic cells used: 13/128 ( 10%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 13/128 ( 10%)
Total shareable expanders not available (n/a): 0/128 ( 0%)
Average fan-in: 2.07
Total fan-in: 27
Total input pins required: 18
Total fast input logic cells required: 0
Total output pins required: 13
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 13
Total flipflops required: 1
Total product terms required: 13
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information:d:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
demo5
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 CLK
1 - - INPUT G 0 0 0 0 0 0 0 RESET
63 (97) (G) INPUT 0 0 0 0 0 2 0 RL0
64 (99) (G) INPUT 0 0 0 0 0 2 0 RL1
65 (101) (G) INPUT 0 0 0 0 0 2 0 RL2
67 (104) (G) INPUT 0 0 0 0 0 2 0 RL3
68 (105) (G) INPUT 0 0 0 0 0 1 0 RL4
69 (107) (G) INPUT 0 0 0 0 0 1 0 RL5
70 (109) (G) INPUT 0 0 0 0 0 1 0 RL6
73 (115) (H) INPUT 0 0 0 0 0 1 0 RL7
33 (64) (D) INPUT 0 0 0 0 0 0 0 SW1
34 (61) (D) INPUT 0 0 0 0 0 0 0 SW2
35 (59) (D) INPUT 0 0 0 0 0 0 0 SW3
36 (57) (D) INPUT 0 0 0 0 0 0 0 SW4
37 (56) (D) INPUT 0 0 0 0 0 0 0 SW5
39 (53) (D) INPUT 0 0 0 0 0 0 0 SW6
40 (51) (D) INPUT 0 0 0 0 0 0 0 SW7
41 (49) (D) INPUT 0 0 0 0 0 0 0 SW8
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:d:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
demo5
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
74 117 H OUTPUT t 0 0 0 1 1 0 0 GL
58 91 F FF + t 0 0 0 0 0 12 0 KB0
9 8 A OUTPUT t 0 0 0 1 1 0 0 LED0
10 6 A OUTPUT t 0 0 0 1 1 0 0 LED1
11 5 A OUTPUT t 0 0 0 1 1 0 0 LED2
12 3 A OUTPUT t 0 0 0 1 1 0 0 LED3
15 29 B OUTPUT t 0 0 0 1 1 0 0 LED4
16 27 B OUTPUT t 0 0 0 1 1 0 0 LED5
17 25 B OUTPUT t 0 0 0 1 1 0 0 LED6
18 24 B OUTPUT t 0 0 0 1 1 0 0 LED7
75 118 H OUTPUT t 0 0 0 1 1 0 0 RL
31 35 C OUTPUT t 0 0 0 1 1 0 0 SPK
76 120 H OUTPUT t 0 0 0 1 1 0 0 YL
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information:d:\eda-240h\altera\7128slc_plcc84\7128_84_vhdl\demo5\demo5.rpt
demo5
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