📄 demo8.rpt
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_X007 = EXP( D0 & !D1);
-- Node name is 'D'
-- Equation name is 'D', location is LC104, type is output.
D = LCELL( _EQ005 $ _EQ006);
_EQ005 = !D4 & D5 & !D6 & D7 & !_LC102 & !SS0 & _X001 & _X002
# D4 & !D5 & !D6 & !D7 & !_LC102 & !SS0 & _X001 & _X002
# !D4 & !D5 & D6 & !D7 & !_LC102 & !SS0 & _X001 & _X002
# !D0 & D1 & !D2 & D3 & !_LC102 & SS0 & _X001 & _X002;
_X001 = EXP(!D0 & !D1 & D2 & !D3 & SS0);
_X002 = EXP( D0 & !D1 & !D2 & !D3 & SS0);
_EQ006 = !_LC102 & _X001 & _X002;
_X001 = EXP(!D0 & !D1 & D2 & !D3 & SS0);
_X002 = EXP( D0 & !D1 & !D2 & !D3 & SS0);
-- Node name is 'E'
-- Equation name is 'E', location is LC105, type is output.
E = LCELL( _EQ007 $ !_LC103);
_EQ007 = D4 & !D5 & !D6 & !_LC103 & !SS0
# !D5 & D6 & !D7 & !_LC103 & !SS0
# D0 & !D1 & !D2 & !_LC103 & SS0
# !D1 & D2 & !D3 & !_LC103 & SS0;
-- Node name is 'F'
-- Equation name is 'F', location is LC107, type is output.
F = LCELL( _EQ008 $ !_LC106);
_EQ008 = D4 & !D5 & D6 & D7 & !_LC106 & !SS0
# D0 & !D1 & D2 & D3 & !_LC106 & SS0
# D4 & D5 & !D7 & !_LC106 & !SS0
# D4 & !D6 & !D7 & !_LC106 & !SS0;
-- Node name is 'G'
-- Equation name is 'G', location is LC109, type is output.
G = LCELL( _EQ009 $ _EQ010);
_EQ009 = D4 & D5 & D6 & !D7 & !SS0 & _X008 & _X009
# !D4 & !D5 & D6 & D7 & !SS0 & _X008 & _X009
# D0 & D1 & D2 & !D3 & SS0 & _X008 & _X009
# !D0 & !D1 & D2 & D3 & SS0 & _X008 & _X009;
_X008 = EXP(!D1 & !D2 & !D3 & SS0);
_X009 = EXP(!D5 & !D6 & !D7 & !SS0);
_EQ010 = _X008 & _X009;
_X008 = EXP(!D1 & !D2 & !D3 & SS0);
_X009 = EXP(!D5 & !D6 & !D7 & !SS0);
-- Node name is 'IO_DS1'
-- Equation name is 'IO_DS1', location is LC126, type is output.
IO_DS1 = LCELL( GND $ GND);
-- Node name is 'IO_DS2'
-- Equation name is 'IO_DS2', location is LC128, type is output.
IO_DS2 = LCELL( GND $ GND);
-- Node name is 'SS0' = '|hb4:40|count' from file "hb4.tdf" line 8, column 4
-- Equation name is 'SS0', type is output
SS0 = _LC091~NOT;
_LC091~NOT = TFFE( VCC, GLOBAL( CKDSP), VCC, VCC, VCC);
-- Node name is 'START' = '|readad:36|:30' from file "readad.tdf" line 8, column 16
-- Equation name is 'START', type is output
START = DFFE( _EQ011 $ _LC082, GLOBAL( CLK), VCC, RESET, VCC);
_EQ011 = _LC082 & !_LC086 & !_LC089 & !_LC090
# !_LC081 & _LC082;
-- Node name is '|DELED:11|~227~1' from file "deled.tdf" line 23, column 20
-- Equation name is '_LC110', type is buried
-- synthesized logic cell
_LC110 = LCELL( _EQ012 $ GND);
_EQ012 = !D0 & !D1 & !D2 & !D3 & !D4 & !D5 & !D6 & !D7
# D4 & D5 & D6 & !D7 & !SS0
# D4 & !D5 & D6 & D7 & !SS0
# D0 & D1 & D2 & !D3 & SS0
# !D4 & D5 & !D6 & D7 & !SS0;
-- Node name is '|DELED:11|~227~2' from file "deled.tdf" line 23, column 20
-- Equation name is '_LC098', type is buried
-- synthesized logic cell
_LC098 = LCELL( _EQ013 $ GND);
_EQ013 = D0 & !D1 & D2 & D3 & SS0
# !D0 & D1 & !D2 & D3 & SS0
# !D5 & !D6 & D7 & !SS0
# !D1 & !D2 & D3 & SS0
# !D6 & !D7 & !SS0;
-- Node name is '|DELED:11|~245~1' from file "deled.tdf" line 24, column 24
-- Equation name is '_LC102', type is buried
-- synthesized logic cell
_LC102 = LCELL( _EQ014 $ GND);
_EQ014 = D4 & D5 & D6 & !SS0
# D0 & D1 & D2 & SS0;
-- Node name is '|DELED:11|~262~1' from file "deled.tdf" line 25, column 26
-- Equation name is '_LC103', type is buried
-- synthesized logic cell
_LC103 = LCELL( _EQ015 $ GND);
_EQ015 = D4 & !D7 & !SS0
# D0 & !D3 & SS0;
-- Node name is '|DELED:11|~264~1' from file "deled.tdf" line 25, column 28
-- Equation name is '_LC106', type is buried
-- synthesized logic cell
_LC106 = LCELL( _EQ016 $ GND);
_EQ016 = D5 & !D6 & !D7 & !SS0
# D0 & D1 & !D3 & SS0
# D0 & !D2 & !D3 & SS0
# D1 & !D2 & !D3 & SS0;
-- Node name is '|readad:36|enout0' from file "readad.tdf" line 8, column 9
-- Equation name is '_LC100', type is buried
_LC100 = DFFE( _EQ017 $ GND, GLOBAL( CLK), RESET, VCC, VCC);
_EQ017 = !_LC086 & !_LC089 & !_LC090 & !_LC100
# !_LC081 & !_LC100
# !_LC082 & !_LC100;
-- Node name is '|readad:36|enout1' from file "readad.tdf" line 8, column 9
-- Equation name is '_LC083', type is buried
_LC083 = DFFE( _EQ018 $ VCC, GLOBAL( CLK), RESET, VCC, VCC);
_EQ018 = _LC081 & _LC082 & _X010
# _LC083 & _LC100
# !_LC083 & !_LC100;
_X010 = EXP(!_LC086 & !_LC089 & !_LC090);
-- Node name is '|readad:36|enout2' from file "readad.tdf" line 8, column 9
-- Equation name is '_LC089', type is buried
_LC089 = TFFE( _EQ019, GLOBAL( CLK), RESET, VCC, VCC);
_EQ019 = _LC083 & !_LC086 & !_LC089 & !_LC090 & _LC100
# _LC083 & !_LC089 & _LC100 & _X011
# _LC083 & _LC089 & _LC100
# _LC081 & _LC082 & _LC089;
_X011 = EXP( _LC081 & _LC082);
-- Node name is '|readad:36|enout3' from file "readad.tdf" line 8, column 9
-- Equation name is '_LC090', type is buried
_LC090 = TFFE( _EQ020, GLOBAL( CLK), RESET, VCC, VCC);
_EQ020 = !_LC082 & _LC083 & _LC089 & !_LC090 & _LC100
# !_LC081 & _LC083 & _LC089 & !_LC090 & _LC100
# _LC083 & _LC089 & _LC090 & _LC100
# _LC081 & _LC082 & _LC090;
-- Node name is '|readad:36|enout4' from file "readad.tdf" line 8, column 9
-- Equation name is '_LC086', type is buried
_LC086 = TFFE( _EQ021, GLOBAL( CLK), RESET, VCC, VCC);
_EQ021 = !_LC082 & _LC083 & !_LC086 & _LC089 & _LC090 & _LC100
# !_LC081 & _LC083 & !_LC086 & _LC089 & _LC090 & _LC100
# _LC083 & _LC086 & _LC089 & _LC090 & _LC100
# _LC081 & _LC082 & _LC086;
-- Node name is '|readad:36|enout5' from file "readad.tdf" line 8, column 9
-- Equation name is '_LC082', type is buried
_LC082 = TFFE( _EQ022, GLOBAL( CLK), RESET, VCC, VCC);
_EQ022 = _LC083 & _LC086 & _LC089 & _LC090 & _LC100
# _LC081 & _LC082 & _LC086
# _LC081 & _LC082 & _LC090
# _LC081 & _LC082 & _LC089;
-- Node name is '|readad:36|enout6' from file "readad.tdf" line 8, column 9
-- Equation name is '_LC081', type is buried
_LC081 = DFFE( _EQ023 $ GND, GLOBAL( CLK), RESET, VCC, VCC);
_EQ023 = !_LC081 & _LC082 & _LC083 & _LC086 & _LC089 & _LC090 &
_LC100
# _LC081 & !_LC086 & !_LC089 & !_LC090
# _LC081 & !_LC082;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\eda-240h\altera\7128_84_vhdl\demo8\demo8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,456K
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