📄 demo8.rpt
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36 (57) (D) INPUT 0 0 0 0 0 0 0 SW3
37 (56) (D) INPUT 0 0 0 0 0 0 0 SW4
39 (53) (D) INPUT 0 0 0 0 0 0 0 SW5
40 (51) (D) INPUT 0 0 0 0 0 0 0 SW6
41 (49) (D) INPUT 0 0 0 0 0 0 0 SW7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo8\demo8.rpt
demo8
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
63 97 G OUTPUT t 5 3 1 8 1 0 0 A
64 99 G OUTPUT t 3 2 0 8 3 0 0 B
65 101 G OUTPUT t 2 0 0 8 1 0 0 C
67 104 G OUTPUT t 3 2 1 8 2 0 0 D
68 105 G OUTPUT t 1 0 1 8 2 0 0 E
69 107 G OUTPUT t 1 0 1 8 2 0 0 F
70 109 G OUTPUT t 3 0 1 8 1 0 0 G
80 126 H OUTPUT t 0 0 0 0 0 0 0 IO_DS1
81 128 H OUTPUT t 0 0 0 0 0 0 0 IO_DS2
58 91 F FF + t ! 0 0 0 0 0 7 5 SS0
60 93 F FF + t 0 0 0 1 5 0 0 START
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo8\demo8.rpt
demo8
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 110 G SOFT s t 1 0 1 8 1 1 0 |DELED:11|~227~1
- 98 G SOFT s t 1 0 1 7 1 1 0 |DELED:11|~227~2
- 102 G SOFT s t 0 0 0 6 1 1 0 |DELED:11|~245~1
- 103 G SOFT s t 0 0 0 4 1 1 0 |DELED:11|~262~1
- 106 G SOFT s t 0 0 0 7 1 1 0 |DELED:11|~264~1
- 100 G DFFE + t 0 0 0 1 6 0 7 |readad:36|enout0
(54) 83 F DFFE + t 1 0 0 1 7 0 6 |readad:36|enout1
- 89 F TFFE + t 2 0 1 1 7 1 7 |readad:36|enout2
- 90 F TFFE + t 1 0 1 1 6 1 7 |readad:36|enout3
(56) 86 F TFFE + t 1 0 1 1 7 1 6 |readad:36|enout4
- 82 F TFFE + t 1 0 1 1 7 1 7 |readad:36|enout5
- 81 F DFFE + t 0 0 0 1 7 1 7 |readad:36|enout6
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo8\demo8.rpt
demo8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+--------------- LC83 |readad:36|enout1
| +------------- LC89 |readad:36|enout2
| | +----------- LC90 |readad:36|enout3
| | | +--------- LC86 |readad:36|enout4
| | | | +------- LC82 |readad:36|enout5
| | | | | +----- LC81 |readad:36|enout6
| | | | | | +--- LC91 SS0
| | | | | | | +- LC93 START
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'F'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC83 -> * * * * * * - - | - - - - - * - - | <-- |readad:36|enout1
LC89 -> * * * * * * - * | - - - - - * * - | <-- |readad:36|enout2
LC90 -> * * * * * * - * | - - - - - * * - | <-- |readad:36|enout3
LC86 -> * * - * * * - * | - - - - - * * - | <-- |readad:36|enout4
LC82 -> * * * * * * - * | - - - - - * * - | <-- |readad:36|enout5
LC81 -> * * * * * * - * | - - - - - * * - | <-- |readad:36|enout6
Pin
83 -> - - - - - - - - | - - - - - - - - | <-- CKDSP
2 -> - - - - - - - - | - - - - - - - - | <-- CLK
1 -> * * * * * * - * | - - - - - * * - | <-- RESET
LC100-> * * * * * * - - | - - - - - * * - | <-- |readad:36|enout0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo8\demo8.rpt
demo8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------------------- LC97 A
| +----------------------- LC99 B
| | +--------------------- LC101 C
| | | +------------------- LC104 D
| | | | +----------------- LC110 |DELED:11|~227~1
| | | | | +--------------- LC98 |DELED:11|~227~2
| | | | | | +------------- LC102 |DELED:11|~245~1
| | | | | | | +----------- LC103 |DELED:11|~262~1
| | | | | | | | +--------- LC106 |DELED:11|~264~1
| | | | | | | | | +------- LC105 E
| | | | | | | | | | +----- LC107 F
| | | | | | | | | | | +--- LC109 G
| | | | | | | | | | | | +- LC100 |readad:36|enout0
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC110-> - * - - - - - - - - - - - | - - - - - - * - | <-- |DELED:11|~227~1
LC98 -> - * - - - - - - - - - - - | - - - - - - * - | <-- |DELED:11|~227~2
LC102-> - - - * - - - - - - - - - | - - - - - - * - | <-- |DELED:11|~245~1
LC103-> - - - - - - - - - * - - - | - - - - - - * - | <-- |DELED:11|~262~1
LC106-> - - - - - - - - - - * - - | - - - - - - * - | <-- |DELED:11|~264~1
LC100-> - - - - - - - - - - - - * | - - - - - * * - | <-- |readad:36|enout0
Pin
83 -> - - - - - - - - - - - - - | - - - - - - - - | <-- CKDSP
2 -> - - - - - - - - - - - - - | - - - - - - - - | <-- CLK
44 -> * * * * * * * * * * * * - | - - - - - - * - | <-- D0
45 -> * * * * * * * - * * * * - | - - - - - - * - | <-- D1
46 -> * * * * * * * - * * * * - | - - - - - - * - | <-- D2
48 -> * * * * * * - * * * * * - | - - - - - - * - | <-- D3
49 -> * * * * * - * * - * * * - | - - - - - - * - | <-- D4
50 -> * * * * * * * - * * * * - | - - - - - - * - | <-- D5
51 -> * * * * * * * - * * * * - | - - - - - - * - | <-- D6
52 -> * * * * * * - * * * * * - | - - - - - - * - | <-- D7
1 -> - - - - - - - - - - - - * | - - - - - * * - | <-- RESET
LC89 -> - - - - - - - - - - - - * | - - - - - * * - | <-- |readad:36|enout2
LC90 -> - - - - - - - - - - - - * | - - - - - * * - | <-- |readad:36|enout3
LC86 -> - - - - - - - - - - - - * | - - - - - * * - | <-- |readad:36|enout4
LC82 -> - - - - - - - - - - - - * | - - - - - * * - | <-- |readad:36|enout5
LC81 -> - - - - - - - - - - - - * | - - - - - * * - | <-- |readad:36|enout6
LC91 -> * * * * * * * * * * * * - | - - - - - - * - | <-- SS0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo8\demo8.rpt
demo8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+--- LC126 IO_DS1
| +- LC128 IO_DS2
| |
| | Other LABs fed by signals
| | that feed LAB 'H'
LC | | | A B C D E F G H | Logic cells that feed LAB 'H':
Pin
83 -> - - | - - - - - - - - | <-- CKDSP
2 -> - - | - - - - - - - - | <-- CLK
1 -> - - | - - - - - * * - | <-- RESET
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo8\demo8.rpt
demo8
** EQUATIONS **
CKDSP : INPUT;
CLK : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
RESET : INPUT;
SW0 : INPUT;
SW1 : INPUT;
SW2 : INPUT;
SW3 : INPUT;
SW4 : INPUT;
SW5 : INPUT;
SW6 : INPUT;
SW7 : INPUT;
-- Node name is 'A'
-- Equation name is 'A', location is LC097, type is output.
A = LCELL( _EQ001 $ _EQ002);
_EQ001 = D4 & !D5 & D6 & D7 & !SS0 & _X001 & _X002 & _X003 & _X004
# D4 & D5 & !D6 & D7 & !SS0 & _X001 & _X002 & _X003 & _X004
# D0 & !D1 & D2 & D3 & SS0 & _X001 & _X002 & _X003 & _X004
# D0 & D1 & !D2 & D3 & SS0 & _X001 & _X002 & _X003 & _X004;
_X001 = EXP(!D0 & !D1 & D2 & !D3 & SS0);
_X002 = EXP( D0 & !D1 & !D2 & !D3 & SS0);
_X003 = EXP(!D4 & !D5 & D6 & !D7 & !SS0);
_X004 = EXP( D4 & !D5 & !D6 & !D7 & !SS0);
_EQ002 = _X001 & _X002 & _X003 & _X004;
_X001 = EXP(!D0 & !D1 & D2 & !D3 & SS0);
_X002 = EXP( D0 & !D1 & !D2 & !D3 & SS0);
_X003 = EXP(!D4 & !D5 & D6 & !D7 & !SS0);
_X004 = EXP( D4 & !D5 & !D6 & !D7 & !SS0);
-- Node name is 'B'
-- Equation name is 'B', location is LC099, type is output.
B = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC098 & !_LC110 & _X001 & _X003 & _X005;
_X001 = EXP(!D0 & !D1 & D2 & !D3 & SS0);
_X003 = EXP(!D4 & !D5 & D6 & !D7 & !SS0);
_X005 = EXP(!D2 & !D3 & SS0);
-- Node name is 'C'
-- Equation name is 'C', location is LC101, type is output.
C = LCELL( _EQ004 $ VCC);
_EQ004 = !D4 & D5 & !D6 & !D7 & !SS0
# !D0 & D1 & !D2 & !D3 & SS0
# D6 & D7 & !SS0 & _X006
# D2 & D3 & SS0 & _X007;
_X006 = EXP( D4 & !D5);
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