⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 demo4.rpt

📁 DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计
💻 RPT
📖 第 1 页 / 共 4 页
字号:

-- Node name is '|XMINUTE:2|LPM_ADD_SUB:554|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC040', type is buried 
_LC040   = LCELL( _LC011 $  _LC002);

-- Node name is '|XMINUTE:2|LPM_ADD_SUB:554|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC015', type is buried 
_LC015   = LCELL( _LC010 $  _EQ029);
  _EQ029 =  _LC002 &  _LC009 &  _LC011;

-- Node name is '|XMINUTE:2|:21' = '|XMINUTE:2|min0' 
-- Equation name is '_LC002', type is buried 
_LC002   = TFFE( VCC,  _LC076, GLOBAL( RESET),  VCC,  VCC);

-- Node name is '|XMINUTE:2|:20' = '|XMINUTE:2|min1~45' 
-- Equation name is '_LC011', type is buried 
_LC011   = DFFE( _EQ030 $  _LC040,  _LC076, GLOBAL( RESET),  VCC,  VCC);
  _EQ030 =  _LC002 & !_LC009 &  _LC010 & !_LC011 &  _LC040;

-- Node name is '|XMINUTE:2|:19' = '|XMINUTE:2|min2' 
-- Equation name is '_LC009', type is buried 
_LC009   = TFFE( _EQ031,  _LC076, GLOBAL( RESET),  VCC,  VCC);
  _EQ031 =  _LC002 &  _LC011;

-- Node name is '|XMINUTE:2|:18' = '|XMINUTE:2|min3' 
-- Equation name is '_LC010', type is buried 
_LC010   = DFFE( _EQ032 $  _LC015,  _LC076, GLOBAL( RESET),  VCC,  VCC);
  _EQ032 =  _LC002 & !_LC009 &  _LC010 & !_LC011 &  _LC015;

-- Node name is '|XMINUTE:2|:17' = '|XMINUTE:2|min4' 
-- Equation name is '_LC012', type is buried 
_LC012   = TFFE( _EQ033,  _LC076, GLOBAL( RESET),  VCC,  VCC);
  _EQ033 =  _LC002 & !_LC009 &  _LC010 & !_LC011;

-- Node name is '|XMINUTE:2|:16' = '|XMINUTE:2|min5' 
-- Equation name is '_LC014', type is buried 
_LC014   = TFFE( _EQ034,  _LC076, GLOBAL( RESET),  VCC,  VCC);
  _EQ034 = !_LC001 &  _LC002 & !_LC009 &  _LC010 & !_LC011 &  _LC012 & 
             !_LC014
         #  _LC002 & !_LC009 &  _LC010 & !_LC011 &  _LC012 &  _LC014;

-- Node name is '|XMINUTE:2|:15' = '|XMINUTE:2|min6' 
-- Equation name is '_LC001', type is buried 
_LC001   = TFFE( _EQ035,  _LC076, GLOBAL( RESET),  VCC,  VCC);
  _EQ035 = !_LC001 &  _LC002 & !_LC009 &  _LC010 & !_LC011 &  _LC012 & 
              _LC014
         #  _LC001 &  _LC002 & !_LC009 &  _LC010 & !_LC011 &  _LC012;

-- Node name is '|XMINUTE:2|:12' 
-- Equation name is '_LC007', type is buried 
_LC007   = DFFE( _EQ036 $  VCC, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ036 = !_LC016 &  SETHOUR;

-- Node name is '|XSECOND:1|:22' = '|XSECOND:1|emin' 
-- Equation name is '_LC083', type is buried 
_LC083   = DFFE( _EQ037 $  GND, GLOBAL( CLK),  VCC,  VCC,  RESET);
  _EQ037 = !_LC067 &  _LC074 &  _LC086 & !_LC087 & !_LC113 &  _LC116 & 
              _LC120;

-- Node name is '|XSECOND:1|LPM_ADD_SUB:553|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC119', type is buried 
_LC119   = LCELL( _LC067 $  _LC116);

-- Node name is '|XSECOND:1|LPM_ADD_SUB:553|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC125', type is buried 
_LC125   = LCELL( _LC074 $  _EQ038);
  _EQ038 =  _LC067 &  _LC113 &  _LC116;

-- Node name is '|XSECOND:1|:21' = '|XSECOND:1|sec0' 
-- Equation name is '_LC116', type is buried 
_LC116   = TFFE( VCC, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);

-- Node name is '|XSECOND:1|:20' = '|XSECOND:1|sec1~45' 
-- Equation name is '_LC067', type is buried 
_LC067   = DFFE( _EQ039 $  _LC119, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ039 = !_LC067 &  _LC074 & !_LC113 &  _LC116 &  _LC119;

-- Node name is '|XSECOND:1|:19' = '|XSECOND:1|sec2' 
-- Equation name is '_LC113', type is buried 
_LC113   = TFFE( _EQ040, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ040 =  _LC067 &  _LC116;

-- Node name is '|XSECOND:1|:18' = '|XSECOND:1|sec3' 
-- Equation name is '_LC074', type is buried 
_LC074   = DFFE( _EQ041 $  _LC125, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ041 = !_LC067 &  _LC074 & !_LC113 &  _LC116 &  _LC125;

-- Node name is '|XSECOND:1|:17' = '|XSECOND:1|sec4' 
-- Equation name is '_LC120', type is buried 
_LC120   = TFFE( _EQ042, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ042 = !_LC067 &  _LC074 & !_LC113 &  _LC116;

-- Node name is '|XSECOND:1|:16' = '|XSECOND:1|sec5' 
-- Equation name is '_LC087', type is buried 
_LC087   = TFFE( _EQ043, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ043 = !_LC067 &  _LC074 & !_LC086 & !_LC087 & !_LC113 &  _LC116 & 
              _LC120
         # !_LC067 &  _LC074 &  _LC087 & !_LC113 &  _LC116 &  _LC120;

-- Node name is '|XSECOND:1|:15' = '|XSECOND:1|sec6' 
-- Equation name is '_LC086', type is buried 
_LC086   = TFFE( _EQ044, GLOBAL( CLK), GLOBAL( RESET),  VCC,  VCC);
  _EQ044 = !_LC067 &  _LC074 & !_LC086 &  _LC087 & !_LC113 &  _LC116 & 
              _LC120
         # !_LC067 &  _LC074 &  _LC086 & !_LC113 &  _LC116 &  _LC120;

-- Node name is '|XSECOND:1|:12' 
-- Equation name is '_LC076', type is buried 
_LC076   = DFFE( _EQ045 $  VCC, GLOBAL( CKDSP), GLOBAL( RESET),  VCC,  VCC);
  _EQ045 = !_LC083 &  SETMIN;

-- Node name is '|XSETTIME:9|:32' = '|XSETTIME:9|sel10' 
-- Equation name is '_LC081', type is buried 
_LC081   = TFFE(!_EQ046, GLOBAL( CKDSP), GLOBAL( RESET),  VCC,  VCC);
  _EQ046 = !_LC081 &  _LC082 &  _LC084;

-- Node name is '|XSETTIME:9|:31' = '|XSETTIME:9|sel11' 
-- Equation name is '_LC082', type is buried 
_LC082   = DFFE( _EQ047 $  GND, GLOBAL( CKDSP), GLOBAL( RESET),  VCC,  VCC);
  _EQ047 = !_LC081 &  _LC082 & !_LC084
         #  _LC081 & !_LC082 & !_LC084;

-- Node name is '|XSETTIME:9|:30' = '|XSETTIME:9|sel12' 
-- Equation name is '_LC084', type is buried 
_LC084   = DFFE( _EQ048 $  GND, GLOBAL( CKDSP), GLOBAL( RESET),  VCC,  VCC);
  _EQ048 =  _LC081 &  _LC082 & !_LC084
         # !_LC081 & !_LC082 &  _LC084;

-- Node name is '|XSETTIME:9|~870~1~2' 
-- Equation name is '_LC096', type is buried 
-- synthesized logic cell 
_LC096   = LCELL( _EQ049 $  GND);
  _EQ049 =  _LC074 &  _LC081 & !_LC082 &  _LC117 &  RESET
         #  _LC074 &  _LC081 &  _LC084 &  _LC090 &  RESET
         #  _LC010 &  _LC081 & !_LC084 &  _LC117 &  RESET
         #  _LC010 &  _LC081 &  _LC082 &  _LC090 &  RESET;

-- Node name is '|XSETTIME:9|~870~1' 
-- Equation name is '_LC090', type is buried 
-- synthesized logic cell 
_LC090   = LCELL( _EQ050 $  GND);
  _EQ050 =  _LC074 &  _LC081 & !_LC082 &  _LC084 &  RESET
         #  _LC010 &  _LC081 &  _LC082 & !_LC084 &  RESET
         #  _LC081 & !_LC082 & !_LC084 &  _LC117 &  RESET
         #  _LC082 &  _LC084 &  _LC090 &  RESET
         #  _LC096;

-- Node name is '|XSETTIME:9|~876~1~2' 
-- Equation name is '_LC085', type is buried 
-- synthesized logic cell 
_LC085   = LCELL( _EQ051 $  GND);
  _EQ051 =  _LC081 &  _LC084 & !_LC092 & !_LC113 &  RESET &  _X004 &  _X005 & 
              _X006
         #  _LC081 & !_LC082 & !_LC113 & !_LC115 &  RESET &  _X004 &  _X005 & 
              _X006
         # !_LC009 &  _LC081 &  _LC082 & !_LC092 &  RESET &  _X004 &  _X005 & 
              _X006
         # !_LC009 &  _LC081 & !_LC084 & !_LC115 &  RESET &  _X004 &  _X005 & 
              _X006
         # !_LC082 & !_LC084 & !_LC115 &  RESET &  _X004 &  _X005 &  _X006;
  _X004  = EXP(!_LC001 & !_LC081 & !_LC084);
  _X005  = EXP(!_LC081 & !_LC082 & !_LC084);
  _X006  = EXP(!_LC081 & !_LC082 & !_LC086);

-- Node name is '|XSETTIME:9|~876~1' 
-- Equation name is '_LC092', type is buried 
-- synthesized logic cell 
_LC092   = LCELL( _EQ052 $  _EQ053);
  _EQ052 =  _LC081 & !_LC082 &  _LC084 & !_LC113 &  RESET &  _X004 &  _X005 & 
              _X006
         # !_LC009 &  _LC081 &  _LC082 & !_LC084 &  RESET &  _X004 &  _X005 & 
              _X006
         #  _LC082 &  _LC084 & !_LC092 &  RESET &  _X004 &  _X005 &  _X006
         #  _LC085;
  _X004  = EXP(!_LC001 & !_LC081 & !_LC084);
  _X005  = EXP(!_LC081 & !_LC082 & !_LC084);
  _X006  = EXP(!_LC081 & !_LC082 & !_LC086);
  _EQ053 =  RESET &  _X004 &  _X005 &  _X006;
  _X004  = EXP(!_LC001 & !_LC081 & !_LC084);
  _X005  = EXP(!_LC081 & !_LC082 & !_LC084);
  _X006  = EXP(!_LC081 & !_LC082 & !_LC086);

-- Node name is '|XSETTIME:9|~882~1' 
-- Equation name is '_LC013', type is buried 
-- synthesized logic cell 
_LC013   = LCELL( _EQ054 $  VCC);
  _EQ054 =  _X007 &  _X008 &  _X009 &  _X010 &  _X011 &  _X012 &  _X013;
  _X007  = EXP( _LC067 &  _LC081 & !_LC082 &  _LC084 &  RESET);
  _X008  = EXP( _LC011 &  _LC081 &  _LC082 & !_LC084 &  RESET);
  _X009  = EXP( _LC081 & !_LC082 & !_LC084 &  _LC114 &  RESET);
  _X010  = EXP( _LC014 & !_LC081 &  _LC082 & !_LC084 &  RESET);
  _X011  = EXP(!_LC081 & !_LC082 &  _LC084 &  _LC087 &  RESET);
  _X012  = EXP(!_LC081 & !_LC082 & !_LC084 &  _LC123 &  RESET);
  _X013  = EXP( _LC013 &  _LC082 &  _LC084 &  RESET);

-- Node name is '|XSETTIME:9|~888~1' 
-- Equation name is '_LC089', type is buried 
-- synthesized logic cell 
_LC089   = LCELL( _EQ055 $  VCC);
  _EQ055 =  _X014 &  _X015 &  _X016 &  _X017 &  _X018 &  _X019 &  _X020;
  _X014  = EXP( _LC081 & !_LC082 &  _LC084 &  _LC116 &  RESET);
  _X015  = EXP( _LC002 &  _LC081 &  _LC082 & !_LC084 &  RESET);
  _X016  = EXP( _LC081 & !_LC082 & !_LC084 &  _LC127 &  RESET);
  _X017  = EXP( _LC012 & !_LC081 &  _LC082 & !_LC084 &  RESET);
  _X018  = EXP(!_LC081 & !_LC082 &  _LC084 &  _LC120 &  RESET);
  _X019  = EXP(!_LC081 & !_LC082 & !_LC084 &  _LC118 &  RESET);
  _X020  = EXP( _LC082 &  _LC084 &  _LC089 &  RESET);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X003 occurs in LABs A, C




Project Information            d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,156K

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -