📄 demo4.rpt
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Logic cells placed in LAB 'G'
+--------------- LC97 A
| +------------- LC99 B
| | +----------- LC101 C
| | | +--------- LC104 D
| | | | +------- LC105 E
| | | | | +----- LC107 F
| | | | | | +--- LC109 G
| | | | | | | +- LC100 |XDELED:10|~400~1
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'G'
LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC100-> - - - - * - - - | - - - - - - * - | <-- |XDELED:10|~400~1
Pin
83 -> - - - - - - - - | - - - - - - - - | <-- CKDSP
2 -> - - - - - - - - | - - - - - - - - | <-- CLK
1 -> - - - - - - - - | * - * - - * - - | <-- RESET
LC90 -> * * * * * * * * | - - - - - * * - | <-- |XSETTIME:9|~870~1
LC92 -> * * * * * * * * | - - - - - * * - | <-- |XSETTIME:9|~876~1
LC13 -> * * * * * * * * | * - - - - - * - | <-- |XSETTIME:9|~882~1
LC89 -> * * * * * * * * | - - - - - * * - | <-- |XSETTIME:9|~888~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC126 IO_DS1
| +----------------------------- LC128 IO_DS2
| | +--------------------------- LC121 |XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node1
| | | +------------------------- LC122 |XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node2
| | | | +----------------------- LC124 |XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node3
| | | | | +--------------------- LC123 |XHOUR:3|hour5
| | | | | | +------------------- LC118 |XHOUR:3|hour4
| | | | | | | +----------------- LC117 |XHOUR:3|hour3
| | | | | | | | +--------------- LC115 |XHOUR:3|hour2
| | | | | | | | | +------------- LC114 |XHOUR:3|hour1
| | | | | | | | | | +----------- LC127 |XHOUR:3|hour0
| | | | | | | | | | | +--------- LC119 |XSECOND:1|LPM_ADD_SUB:553|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | | | | +------- LC125 |XSECOND:1|LPM_ADD_SUB:553|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | | | | +----- LC120 |XSECOND:1|sec4
| | | | | | | | | | | | | | +--- LC113 |XSECOND:1|sec2
| | | | | | | | | | | | | | | +- LC116 |XSECOND:1|sec0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC121-> - - - - - - - - - * - - - - - - | - - - - - - - * | <-- |XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node1
LC122-> - - - - - - - - * - - - - - - - | - - - - - - - * | <-- |XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node2
LC124-> - - - - - - - * - - - - - - - - | - - - - - - - * | <-- |XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node3
LC123-> - - - - - * - * * * - - - - - - | * - - - - - - * | <-- |XHOUR:3|hour5
LC118-> - - - - - * * * * * - - - - - - | - - - - - * - * | <-- |XHOUR:3|hour4
LC117-> - - - - * * * * * * - - - - - - | - - - - - * - * | <-- |XHOUR:3|hour3
LC115-> - - - * * * * * * * - - - - - - | - - - - - * - * | <-- |XHOUR:3|hour2
LC114-> - - * * * * * * * * - - - - - - | * - - - - - - * | <-- |XHOUR:3|hour1
LC127-> - - * * * * * * * * * - - - - - | - - - - - * - * | <-- |XHOUR:3|hour0
LC113-> - - - - - - - - - - - - * * * - | - - - - * * - * | <-- |XSECOND:1|sec2
LC116-> - - - - - - - - - - - * * * * * | - - - - * * - * | <-- |XSECOND:1|sec0
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- CKDSP
2 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- CLK
1 -> - - - - - - - - - - - - - - - - | * - * - - * - - | <-- RESET
LC7 -> - - - - - * * * * * * - - - - - | - - - - - - - * | <-- |XMINUTE:2|:12
LC74 -> - - - - - - - - - - - - * * - - | - - - - * * - * | <-- |XSECOND:1|sec3
LC67 -> - - - - - - - - - - - * * * * - | * - - - * * - * | <-- |XSECOND:1|sec1~45
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** EQUATIONS **
CKDSP : INPUT;
CLK : INPUT;
RESET : INPUT;
SETHOUR : INPUT;
SETMIN : INPUT;
SW1 : INPUT;
SW2 : INPUT;
SW3 : INPUT;
SW4 : INPUT;
SW5 : INPUT;
SW6 : INPUT;
SW7 : INPUT;
SW8 : INPUT;
-- Node name is 'A'
-- Equation name is 'A', location is LC097, type is output.
A = LCELL( _EQ001 $ VCC);
_EQ001 = !_LC013 & _LC089 & _LC090 & _LC092 & _X001
# _LC013 & _LC089 & _LC090 & !_LC092 & _X001
# !_LC013 & !_LC089 & !_LC090 & _LC092 & _X001
# !_LC013 & _LC089 & !_LC090 & !_LC092 & _X001;
_X001 = EXP(!_LC013 & !_LC089 & !_LC090 & !_LC092);
-- Node name is 'B'
-- Equation name is 'B', location is LC099, type is output.
B = LCELL( _EQ002 $ VCC);
_EQ002 = _LC013 & _LC089 & _LC090 & _X001 & _X002
# _LC013 & !_LC089 & _LC092 & _X001 & _X002
# !_LC089 & _LC090 & _LC092 & _X001 & _X002
# !_LC013 & _LC089 & !_LC090 & _X001 & _X002
# !_LC013 & !_LC090 & !_LC092 & _X001 & _X002;
_X001 = EXP(!_LC013 & !_LC089 & !_LC090 & !_LC092);
_X002 = EXP(!_LC013 & _LC089 & !_LC090 & !_LC092);
-- Node name is 'C'
-- Equation name is 'C', location is LC101, type is output.
C = LCELL( _EQ003 $ VCC);
_EQ003 = _LC013 & _LC090 & _LC092 & _X001 & _X002
# !_LC089 & _LC090 & _LC092 & _X001 & _X002
# !_LC089 & !_LC090 & !_LC092 & _X001 & _X002
# !_LC013 & !_LC090 & !_LC092 & _X001 & _X002;
_X001 = EXP(!_LC013 & !_LC089 & !_LC090 & !_LC092);
_X002 = EXP(!_LC013 & _LC089 & !_LC090 & !_LC092);
-- Node name is 'D'
-- Equation name is 'D', location is LC104, type is output.
D = LCELL( _EQ004 $ VCC);
_EQ004 = _LC013 & !_LC089 & _LC090 & !_LC092 & _X001
# _LC013 & _LC089 & _LC092 & _X001
# !_LC013 & !_LC089 & !_LC090 & _X001
# !_LC013 & !_LC090 & !_LC092 & _X001;
_X001 = EXP(!_LC013 & !_LC089 & !_LC090 & !_LC092);
-- Node name is 'E'
-- Equation name is 'E', location is LC105, type is output.
E = LCELL( _EQ005 $ GND);
_EQ005 = !_LC013 & !_LC089 & !_LC090 & !_LC092
# _LC100 & _X001 & _X002;
_X001 = EXP(!_LC013 & !_LC089 & !_LC090 & !_LC092);
_X002 = EXP(!_LC013 & _LC089 & !_LC090 & !_LC092);
-- Node name is 'F'
-- Equation name is 'F', location is LC107, type is output.
F = LCELL( _EQ006 $ VCC);
_EQ006 = !_LC013 & _LC089 & _LC090 & _LC092 & _X001
# _LC013 & !_LC089 & !_LC090 & !_LC092 & _X001
# !_LC013 & _LC089 & !_LC090 & !_LC092 & _X001
# _LC013 & _LC089 & !_LC090 & _X001;
_X001 = EXP(!_LC013 & !_LC089 & !_LC090 & !_LC092);
-- Node name is 'G'
-- Equation name is 'G', location is LC109, type is output.
G = LCELL( _EQ007 $ _EQ008);
_EQ007 = _LC013 & _LC089 & !_LC090 & _LC092 & _X001
# !_LC013 & !_LC089 & _LC090 & _LC092 & _X001
# !_LC013 & _LC089 & !_LC090 & !_LC092 & _X001;
_X001 = EXP(!_LC013 & !_LC089 & !_LC090 & !_LC092);
_EQ008 = _X001;
_X001 = EXP(!_LC013 & !_LC089 & !_LC090 & !_LC092);
-- Node name is 'IO_DS1'
-- Equation name is 'IO_DS1', location is LC126, type is output.
IO_DS1 = LCELL( GND $ GND);
-- Node name is 'IO_DS2'
-- Equation name is 'IO_DS2', location is LC128, type is output.
IO_DS2 = LCELL( GND $ GND);
-- Node name is 'IO_DS7'
-- Equation name is 'IO_DS7', location is LC037, type is output.
IO_DS7 = LCELL( GND $ GND);
-- Node name is 'LAMP0'
-- Equation name is 'LAMP0', location is LC008, type is output.
LAMP0 = LCELL( _EQ009 $ GND);
_EQ009 = !_LC001 & !_LC002 & !_LC003 & _LC004 & !_LC009 & !_LC010 &
!_LC011 & !_LC012 & !_LC014
# !_LC003 & _LC004 & !RESET;
-- Node name is 'LAMP1'
-- Equation name is 'LAMP1', location is LC006, type is output.
LAMP1 = LCELL( _EQ010 $ GND);
_EQ010 = !_LC001 & !_LC002 & _LC003 & !_LC004 & !_LC009 & !_LC010 &
!_LC011 & !_LC012 & !_LC014
# _LC003 & !_LC004 & !RESET;
-- Node name is 'LAMP2'
-- Equation name is 'LAMP2', location is LC005, type is output.
LAMP2 = LCELL( _EQ011 $ GND);
_EQ011 = !_LC001 & !_LC002 & _LC003 & _LC004 & !_LC009 & !_LC010 &
!_LC011 & !_LC012 & !_LC014
# _LC003 & _LC004 & !RESET;
-- Node name is 'SPEAK' = '|XALERT:8|:9'
-- Equation name is 'SPEAK', type is output
SPEAK = DFFE( GND $ VCC, GLOBAL( CLK), !_EQ012, VCC, VCC);
_EQ012 = RESET & _X003;
_X003 = EXP(!_LC001 & !_LC002 & !_LC009 & !_LC010 & !_LC011 & !_LC012 &
!_LC014);
-- Node name is 'SS0'
-- Equation name is 'SS0', location is LC091, type is output.
SS0 = LCELL( _EQ013 $ RESET);
_EQ013 = !_LC081 & RESET;
-- Node name is 'SS1'
-- Equation name is 'SS1', location is LC093, type is output.
SS1 = LCELL( _EQ014 $ RESET);
_EQ014 = !_LC082 & RESET;
-- Node name is 'SS2'
-- Equation name is 'SS2', location is LC094, type is output.
SS2 = LCELL( _EQ015 $ RESET);
_EQ015 = !_LC084 & RESET;
-- Node name is '|XALERT:8|:17' = '|XALERT:8|current_state0'
-- Equation name is '_LC004', type is buried
_LC004 = DFFE( _EQ016 $ GND, GLOBAL( CLK), !_EQ017, VCC, VCC);
_EQ016 = !_LC001 & !_LC002 & !_LC004 & !_LC009 & !_LC010 & !_LC011 &
!_LC012 & !_LC014
# !_LC004 & !RESET;
_EQ017 = RESET & _X003;
_X003 = EXP(!_LC001 & !_LC002 & !_LC009 & !_LC010 & !_LC011 & !_LC012 &
!_LC014);
-- Node name is '|XALERT:8|:16' = '|XALERT:8|current_state1'
-- Equation name is '_LC003', type is buried
_LC003 = DFFE( _EQ018 $ GND, GLOBAL( CLK), !_EQ019, VCC, VCC);
_EQ018 = !_LC001 & !_LC002 & !_LC003 & _LC004 & !_LC009 & !_LC010 &
!_LC011 & !_LC012 & !_LC014
# !_LC001 & !_LC002 & _LC003 & !_LC004 & !_LC009 & !_LC010 &
!_LC011 & !_LC012 & !_LC014
# !_LC003 & _LC004 & !RESET
# _LC003 & !_LC004 & !RESET;
_EQ019 = RESET & _X003;
_X003 = EXP(!_LC001 & !_LC002 & !_LC009 & !_LC010 & !_LC011 & !_LC012 &
!_LC014);
-- Node name is '|XDELED:10|~400~1'
-- Equation name is '_LC100', type is buried
-- synthesized logic cell
_LC100 = LCELL( _EQ020 $ VCC);
_EQ020 = !_LC013 & _LC089 & _LC090 & !_LC092
# _LC013 & _LC089 & !_LC090
# !_LC013 & !_LC090 & _LC092;
-- Node name is '|XHOUR:3|:14' = '|XHOUR:3|hour0'
-- Equation name is '_LC127', type is buried
_LC127 = TFFE( VCC, _LC007, GLOBAL( RESET), VCC, VCC);
-- Node name is '|XHOUR:3|:13' = '|XHOUR:3|hour1'
-- Equation name is '_LC114', type is buried
_LC114 = DFFE( _EQ021 $ _LC121, _LC007, GLOBAL( RESET), VCC, VCC);
_EQ021 = _LC114 & !_LC115 & !_LC117 & !_LC118 & _LC121 & _LC123 &
_LC127
# !_LC114 & !_LC115 & _LC117 & _LC121 & _LC127;
-- Node name is '|XHOUR:3|:12' = '|XHOUR:3|hour2'
-- Equation name is '_LC115', type is buried
_LC115 = DFFE( _EQ022 $ _LC122, _LC007, GLOBAL( RESET), VCC, VCC);
_EQ022 = _LC114 & !_LC115 & !_LC117 & !_LC118 & _LC122 & _LC123 &
_LC127
# !_LC114 & !_LC115 & _LC117 & _LC122 & _LC127;
-- Node name is '|XHOUR:3|:11' = '|XHOUR:3|hour3'
-- Equation name is '_LC117', type is buried
_LC117 = DFFE( _EQ023 $ _LC124, _LC007, GLOBAL( RESET), VCC, VCC);
_EQ023 = _LC114 & !_LC115 & !_LC117 & !_LC118 & _LC123 & _LC124 &
_LC127
# !_LC114 & !_LC115 & _LC117 & _LC124 & _LC127;
-- Node name is '|XHOUR:3|:10' = '|XHOUR:3|hour4'
-- Equation name is '_LC118', type is buried
_LC118 = TFFE( _EQ024, _LC007, GLOBAL( RESET), VCC, VCC);
_EQ024 = !_LC114 & !_LC115 & _LC117 & _LC127;
-- Node name is '|XHOUR:3|:9' = '|XHOUR:3|hour5'
-- Equation name is '_LC123', type is buried
_LC123 = TFFE( _EQ025, _LC007, GLOBAL( RESET), VCC, VCC);
_EQ025 = _LC114 & !_LC115 & !_LC117 & !_LC118 & _LC123 & _LC127
# !_LC114 & !_LC115 & _LC117 & _LC118 & _LC127;
-- Node name is '|XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC121', type is buried
_LC121 = LCELL( _LC114 $ _LC127);
-- Node name is '|XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC122', type is buried
_LC122 = LCELL( _LC115 $ _EQ026);
_EQ026 = _LC114 & _LC127;
-- Node name is '|XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC124', type is buried
_LC124 = LCELL( _LC117 $ _EQ027);
_EQ027 = _LC114 & _LC115 & _LC127;
-- Node name is '|XMINUTE:2|:22' = '|XMINUTE:2|ehour'
-- Equation name is '_LC016', type is buried
_LC016 = DFFE( _EQ028 $ GND, _LC076, VCC, VCC, VCC);
_EQ028 = _LC001 & _LC002 & !_LC009 & _LC010 & !_LC011 & _LC012 &
!_LC014 & RESET
# _LC016 & !RESET;
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