📄 demo4.rpt
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Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
63 97 G OUTPUT t 1 1 0 0 4 0 0 A
64 99 G OUTPUT t 3 2 1 0 4 0 0 B
65 101 G OUTPUT t 2 2 0 0 4 0 0 C
67 104 G OUTPUT t 1 1 0 0 4 0 0 D
68 105 G OUTPUT t 2 2 0 0 5 0 0 E
69 107 G OUTPUT t 1 1 0 0 4 0 0 F
70 109 G OUTPUT t 1 1 0 0 4 0 0 G
80 126 H OUTPUT t 0 0 0 0 0 0 0 IO_DS1
81 128 H OUTPUT t 0 0 0 0 0 0 0 IO_DS2
30 37 C OUTPUT t 0 0 0 0 0 0 0 IO_DS7
9 8 A OUTPUT t 0 0 0 1 9 0 0 LAMP0
10 6 A OUTPUT t 0 0 0 1 9 0 0 LAMP1
11 5 A OUTPUT t 0 0 0 1 9 0 0 LAMP2
31 35 C FF + t 1 1 0 1 7 0 0 SPEAK
58 91 F OUTPUT t 0 0 0 1 1 0 0 SS0
60 93 F OUTPUT t 0 0 0 1 1 0 0 SS1
61 94 F OUTPUT t 0 0 0 1 1 0 0 SS2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(12) 3 A DFFE + t 2 1 1 1 9 3 1 |XALERT:8|current_state1 (|XALERT:8|:16)
- 4 A DFFE + t 1 1 0 1 8 3 2 |XALERT:8|current_state0 (|XALERT:8|:17)
- 100 G SOFT s t 0 0 0 0 4 1 0 |XDELED:10|~400~1
- 121 H SOFT t 0 0 0 0 2 0 1 |XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node1
- 122 H SOFT t 0 0 0 0 3 0 1 |XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node2
- 124 H SOFT t 0 0 0 0 4 0 1 |XHOUR:3|LPM_ADD_SUB:280|addcore:adder|addcore:adder0|result_node3
(77) 123 H TFFE t 0 0 0 0 7 0 5 |XHOUR:3|hour5 (|XHOUR:3|:9)
(75) 118 H TFFE t 0 0 0 0 5 0 5 |XHOUR:3|hour4 (|XHOUR:3|:10)
(74) 117 H DFFE t 0 0 0 0 8 0 8 |XHOUR:3|hour3 (|XHOUR:3|:11)
(73) 115 H DFFE t 0 0 0 0 8 0 8 |XHOUR:3|hour2 (|XHOUR:3|:12)
- 114 H DFFE t 0 0 0 0 8 0 9 |XHOUR:3|hour1 (|XHOUR:3|:13)
- 127 H TFFE t 0 0 0 0 1 0 9 |XHOUR:3|hour0 (|XHOUR:3|:14)
(28) 40 C SOFT t 0 0 0 0 2 0 1 |XMINUTE:2|LPM_ADD_SUB:554|addcore:adder|addcore:adder0|result_node1
- 15 A SOFT t 0 0 0 0 4 0 1 |XMINUTE:2|LPM_ADD_SUB:554|addcore:adder|addcore:adder0|result_node3
- 7 A DFFE + t 0 0 0 1 1 0 6 |XMINUTE:2|:12
- 1 A TFFE t 0 0 0 0 8 4 7 |XMINUTE:2|min6 (|XMINUTE:2|:15)
(5) 14 A TFFE t 0 0 0 0 8 4 6 |XMINUTE:2|min5 (|XMINUTE:2|:16)
- 12 A TFFE t 0 0 0 0 5 4 6 |XMINUTE:2|min4 (|XMINUTE:2|:17)
- 10 A DFFE t 0 0 0 0 6 4 11 |XMINUTE:2|min3 (|XMINUTE:2|:18)
- 9 A TFFE t 0 0 0 0 3 4 11 |XMINUTE:2|min2 (|XMINUTE:2|:19)
(8) 11 A DFFE t 0 0 0 0 6 4 12 |XMINUTE:2|min1~45 (|XMINUTE:2|:20)
- 2 A TFFE t 0 0 0 0 1 4 12 |XMINUTE:2|min0 (|XMINUTE:2|:21)
(4) 16 A DFFE t 0 0 0 1 9 0 2 |XMINUTE:2|ehour (|XMINUTE:2|:22)
- 119 H SOFT t 0 0 0 0 2 0 1 |XSECOND:1|LPM_ADD_SUB:553|addcore:adder|addcore:adder0|result_node1
(79) 125 H SOFT t 0 0 0 0 4 0 1 |XSECOND:1|LPM_ADD_SUB:553|addcore:adder|addcore:adder0|result_node3
- 76 E DFFE + t 0 0 0 1 1 0 8 |XSECOND:1|:12
(56) 86 F TFFE + t 0 0 0 0 7 0 5 |XSECOND:1|sec6 (|XSECOND:1|:15)
- 87 F TFFE + t 0 0 0 0 7 0 4 |XSECOND:1|sec5 (|XSECOND:1|:16)
(76) 120 H TFFE + t 0 0 0 0 4 0 4 |XSECOND:1|sec4 (|XSECOND:1|:17)
- 74 E DFFE + t 0 0 0 0 5 0 9 |XSECOND:1|sec3 (|XSECOND:1|:18)
- 113 H TFFE + t 0 0 0 0 2 0 9 |XSECOND:1|sec2 (|XSECOND:1|:19)
(45) 67 E DFFE + t 0 0 0 0 5 0 10 |XSECOND:1|sec1~45 (|XSECOND:1|:20)
- 116 H TFFE + t 0 0 0 0 0 0 10 |XSECOND:1|sec0 (|XSECOND:1|:21)
(54) 83 F DFFE + t 0 0 0 1 7 0 1 |XSECOND:1|emin (|XSECOND:1|:22)
- 84 F DFFE + t 0 0 0 0 3 1 9 |XSETTIME:9|sel12 (|XSETTIME:9|:30)
- 82 F DFFE + t 0 0 0 0 3 1 9 |XSETTIME:9|sel11 (|XSETTIME:9|:31)
- 81 F TFFE + t 0 0 0 0 3 1 9 |XSETTIME:9|sel10 (|XSETTIME:9|:32)
(62) 96 F LCELL s t 0 0 0 1 7 0 1 |XSETTIME:9|~870~1~2
- 90 F LCELL s t 1 0 1 1 8 7 3 |XSETTIME:9|~870~1
(55) 85 F LCELL s t 4 3 1 1 9 0 1 |XSETTIME:9|~876~1~2
- 92 F LCELL s t 4 3 1 1 9 7 3 |XSETTIME:9|~876~1
(6) 13 A LCELL s t 7 0 0 1 10 7 2 |XSETTIME:9|~882~1
- 89 F LCELL s t 7 0 0 1 10 7 2 |XSETTIME:9|~888~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC8 LAMP0
| +----------------------------- LC6 LAMP1
| | +--------------------------- LC5 LAMP2
| | | +------------------------- LC3 |XALERT:8|current_state1
| | | | +----------------------- LC4 |XALERT:8|current_state0
| | | | | +--------------------- LC15 |XMINUTE:2|LPM_ADD_SUB:554|addcore:adder|addcore:adder0|result_node3
| | | | | | +------------------- LC7 |XMINUTE:2|:12
| | | | | | | +----------------- LC1 |XMINUTE:2|min6
| | | | | | | | +--------------- LC14 |XMINUTE:2|min5
| | | | | | | | | +------------- LC12 |XMINUTE:2|min4
| | | | | | | | | | +----------- LC10 |XMINUTE:2|min3
| | | | | | | | | | | +--------- LC9 |XMINUTE:2|min2
| | | | | | | | | | | | +------- LC11 |XMINUTE:2|min1~45
| | | | | | | | | | | | | +----- LC2 |XMINUTE:2|min0
| | | | | | | | | | | | | | +--- LC16 |XMINUTE:2|ehour
| | | | | | | | | | | | | | | +- LC13 |XSETTIME:9|~882~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':
LC3 -> * * * * - - - - - - - - - - - - | * - - - - - - - | <-- |XALERT:8|current_state1
LC4 -> * * * * * - - - - - - - - - - - | * - - - - - - - | <-- |XALERT:8|current_state0
LC15 -> - - - - - - - - - - * - - - - - | * - - - - - - - | <-- |XMINUTE:2|LPM_ADD_SUB:554|addcore:adder|addcore:adder0|result_node3
LC1 -> * * * * * - - * * - - - - - * - | * - * - - * - - | <-- |XMINUTE:2|min6
LC14 -> * * * * * - - * * - - - - - * * | * - * - - - - - | <-- |XMINUTE:2|min5
LC12 -> * * * * * - - * * * - - - - * - | * - * - - * - - | <-- |XMINUTE:2|min4
LC10 -> * * * * * * - * * * * - * - * - | * - * - - * - - | <-- |XMINUTE:2|min3
LC9 -> * * * * * * - * * * * * * - * - | * - * - - * - - | <-- |XMINUTE:2|min2
LC11 -> * * * * * * - * * * * * * - * * | * - * - - - - - | <-- |XMINUTE:2|min1~45
LC2 -> * * * * * * - * * * * * * * * - | * - * - - * - - | <-- |XMINUTE:2|min0
LC16 -> - - - - - - * - - - - - - - * - | * - - - - - - - | <-- |XMINUTE:2|ehour
LC13 -> - - - - - - - - - - - - - - - * | * - - - - - * - | <-- |XSETTIME:9|~882~1
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- CKDSP
2 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- CLK
1 -> * * * * * - - - - - - - - - * * | * - * - - * - - | <-- RESET
73 -> - - - - - - * - - - - - - - - - | * - - - - - - - | <-- SETHOUR
LC123-> - - - - - - - - - - - - - - - * | * - - - - - - * | <-- |XHOUR:3|hour5
LC114-> - - - - - - - - - - - - - - - * | * - - - - - - * | <-- |XHOUR:3|hour1
LC40 -> - - - - - - - - - - - - * - - - | * - - - - - - - | <-- |XMINUTE:2|LPM_ADD_SUB:554|addcore:adder|addcore:adder0|result_node1
LC76 -> - - - - - - - * * * * * * * * - | * - - - - - - - | <-- |XSECOND:1|:12
LC87 -> - - - - - - - - - - - - - - - * | * - - - - * - - | <-- |XSECOND:1|sec5
LC67 -> - - - - - - - - - - - - - - - * | * - - - * * - * | <-- |XSECOND:1|sec1~45
LC84 -> - - - - - - - - - - - - - - - * | * - - - - * - - | <-- |XSETTIME:9|sel12
LC82 -> - - - - - - - - - - - - - - - * | * - - - - * - - | <-- |XSETTIME:9|sel11
LC81 -> - - - - - - - - - - - - - - - * | * - - - - * - - | <-- |XSETTIME:9|sel10
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----- LC37 IO_DS7
| +--- LC35 SPEAK
| | +- LC40 |XMINUTE:2|LPM_ADD_SUB:554|addcore:adder|addcore:adder0|result_node1
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'C'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'C':
Pin
83 -> - - - | - - - - - - - - | <-- CKDSP
2 -> - - - | - - - - - - - - | <-- CLK
1 -> - * - | * - * - - * - - | <-- RESET
LC1 -> - * - | * - * - - * - - | <-- |XMINUTE:2|min6
LC14 -> - * - | * - * - - - - - | <-- |XMINUTE:2|min5
LC12 -> - * - | * - * - - * - - | <-- |XMINUTE:2|min4
LC10 -> - * - | * - * - - * - - | <-- |XMINUTE:2|min3
LC9 -> - * - | * - * - - * - - | <-- |XMINUTE:2|min2
LC11 -> - * * | * - * - - - - - | <-- |XMINUTE:2|min1~45
LC2 -> - * * | * - * - - * - - | <-- |XMINUTE:2|min0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+----- LC76 |XSECOND:1|:12
| +--- LC74 |XSECOND:1|sec3
| | +- LC67 |XSECOND:1|sec1~45
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'E'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'E':
LC74 -> - * * | - - - - * * - * | <-- |XSECOND:1|sec3
LC67 -> - * * | * - - - * * - * | <-- |XSECOND:1|sec1~45
Pin
83 -> - - - | - - - - - - - - | <-- CKDSP
2 -> - - - | - - - - - - - - | <-- CLK
1 -> - - - | * - * - - * - - | <-- RESET
74 -> * - - | - - - - * - - - | <-- SETMIN
LC119-> - - * | - - - - * - - - | <-- |XSECOND:1|LPM_ADD_SUB:553|addcore:adder|addcore:adder0|result_node1
LC125-> - * - | - - - - * - - - | <-- |XSECOND:1|LPM_ADD_SUB:553|addcore:adder|addcore:adder0|result_node3
LC113-> - * * | - - - - * * - * | <-- |XSECOND:1|sec2
LC116-> - * * | - - - - * * - * | <-- |XSECOND:1|sec0
LC83 -> * - - | - - - - * - - - | <-- |XSECOND:1|emin
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+--------------------------- LC91 SS0
| +------------------------- LC93 SS1
| | +----------------------- LC94 SS2
| | | +--------------------- LC86 |XSECOND:1|sec6
| | | | +------------------- LC87 |XSECOND:1|sec5
| | | | | +----------------- LC83 |XSECOND:1|emin
| | | | | | +--------------- LC84 |XSETTIME:9|sel12
| | | | | | | +------------- LC82 |XSETTIME:9|sel11
| | | | | | | | +----------- LC81 |XSETTIME:9|sel10
| | | | | | | | | +--------- LC96 |XSETTIME:9|~870~1~2
| | | | | | | | | | +------- LC90 |XSETTIME:9|~870~1
| | | | | | | | | | | +----- LC85 |XSETTIME:9|~876~1~2
| | | | | | | | | | | | +--- LC92 |XSETTIME:9|~876~1
| | | | | | | | | | | | | +- LC89 |XSETTIME:9|~888~1
| | | | | | | | | | | | | |
| | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC86 -> - - - * * * - - - - - * * - | - - - - - * - - | <-- |XSECOND:1|sec6
LC87 -> - - - * * * - - - - - - - - | * - - - - * - - | <-- |XSECOND:1|sec5
LC84 -> - - * - - - * * * * * * * * | * - - - - * - - | <-- |XSETTIME:9|sel12
LC82 -> - * - - - - * * * * * * * * | * - - - - * - - | <-- |XSETTIME:9|sel11
LC81 -> * - - - - - * * * * * * * * | * - - - - * - - | <-- |XSETTIME:9|sel10
LC96 -> - - - - - - - - - - * - - - | - - - - - * - - | <-- |XSETTIME:9|~870~1~2
LC90 -> - - - - - - - - - * * - - - | - - - - - * * - | <-- |XSETTIME:9|~870~1
LC85 -> - - - - - - - - - - - - * - | - - - - - * - - | <-- |XSETTIME:9|~876~1~2
LC92 -> - - - - - - - - - - - * * - | - - - - - * * - | <-- |XSETTIME:9|~876~1
LC89 -> - - - - - - - - - - - - - * | - - - - - * * - | <-- |XSETTIME:9|~888~1
Pin
83 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- CKDSP
2 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- CLK
1 -> * * * - - * - - - * * * * * | * - * - - * - - | <-- RESET
LC118-> - - - - - - - - - - - - - * | - - - - - * - * | <-- |XHOUR:3|hour4
LC117-> - - - - - - - - - * * - - - | - - - - - * - * | <-- |XHOUR:3|hour3
LC115-> - - - - - - - - - - - * - - | - - - - - * - * | <-- |XHOUR:3|hour2
LC127-> - - - - - - - - - - - - - * | - - - - - * - * | <-- |XHOUR:3|hour0
LC1 -> - - - - - - - - - - - * * - | * - * - - * - - | <-- |XMINUTE:2|min6
LC12 -> - - - - - - - - - - - - - * | * - * - - * - - | <-- |XMINUTE:2|min4
LC10 -> - - - - - - - - - * * - - - | * - * - - * - - | <-- |XMINUTE:2|min3
LC9 -> - - - - - - - - - - - * * - | * - * - - * - - | <-- |XMINUTE:2|min2
LC2 -> - - - - - - - - - - - - - * | * - * - - * - - | <-- |XMINUTE:2|min0
LC120-> - - - * * * - - - - - - - * | - - - - - * - - | <-- |XSECOND:1|sec4
LC74 -> - - - * * * - - - * * - - - | - - - - * * - * | <-- |XSECOND:1|sec3
LC113-> - - - * * * - - - - - * * - | - - - - * * - * | <-- |XSECOND:1|sec2
LC67 -> - - - * * * - - - - - - - - | * - - - * * - * | <-- |XSECOND:1|sec1~45
LC116-> - - - * * * - - - - - - - * | - - - - * * - * | <-- |XSECOND:1|sec0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
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