📄 demo4.rpt
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Project Information d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/15/2004 09:15:58
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
demo4 EPM7128SLC84-6 13 17 0 60 21 46 %
User Pins: 13 17 0
Project Information d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
** PROJECT COMPILATION MESSAGES **
Warning: GLOBAL primitive on node 'RESET' feeds logic -- non-global signal usage may result
Warning: Primitive 'IO_DS2' is stuck at GND
Warning: Primitive 'IO_DS1' is stuck at GND
Warning: Primitive 'IO_DS7' is stuck at GND
Info: Reserved unused input pin 'SW7' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW8' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW6' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW4' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW5' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW1' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'SW2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Project Information d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CKDSP' chosen for auto global Clock
INFO: Signal 'CLK' chosen for auto global Clock
INFO: Signal 'RESET' chosen for auto global Clear
Project Information d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
demo4@63 A
demo4@64 B
demo4@65 C
demo4@83 CKDSP
demo4@2 CLK
demo4@67 D
demo4@68 E
demo4@69 F
demo4@70 G
demo4@80 IO_DS1
demo4@81 IO_DS2
demo4@30 IO_DS7
demo4@9 LAMP0
demo4@10 LAMP1
demo4@11 LAMP2
demo4@1 RESET
demo4@73 SETHOUR
demo4@74 SETMIN
demo4@31 SPEAK
demo4@58 SS0
demo4@60 SS1
demo4@61 SS2
demo4@33 SW1
demo4@34 SW2
demo4@35 SW3
demo4@36 SW4
demo4@37 SW5
demo4@39 SW6
demo4@40 SW7
demo4@41 SW8
Project Information d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
** FILE HIERARCHY **
|xsecond:1|
|xsecond:1|lpm_add_sub:388|
|xsecond:1|lpm_add_sub:388|addcore:adder|
|xsecond:1|lpm_add_sub:388|addcore:adder|addcore:adder0|
|xsecond:1|lpm_add_sub:388|altshift:result_ext_latency_ffs|
|xsecond:1|lpm_add_sub:388|altshift:carry_ext_latency_ffs|
|xsecond:1|lpm_add_sub:388|altshift:oflow_ext_latency_ffs|
|xsecond:1|lpm_add_sub:553|
|xsecond:1|lpm_add_sub:553|addcore:adder|
|xsecond:1|lpm_add_sub:553|addcore:adder|addcore:adder0|
|xsecond:1|lpm_add_sub:553|altshift:result_ext_latency_ffs|
|xsecond:1|lpm_add_sub:553|altshift:carry_ext_latency_ffs|
|xsecond:1|lpm_add_sub:553|altshift:oflow_ext_latency_ffs|
|xminute:2|
|xminute:2|lpm_add_sub:389|
|xminute:2|lpm_add_sub:389|addcore:adder|
|xminute:2|lpm_add_sub:389|addcore:adder|addcore:adder0|
|xminute:2|lpm_add_sub:389|altshift:result_ext_latency_ffs|
|xminute:2|lpm_add_sub:389|altshift:carry_ext_latency_ffs|
|xminute:2|lpm_add_sub:389|altshift:oflow_ext_latency_ffs|
|xminute:2|lpm_add_sub:554|
|xminute:2|lpm_add_sub:554|addcore:adder|
|xminute:2|lpm_add_sub:554|addcore:adder|addcore:adder0|
|xminute:2|lpm_add_sub:554|altshift:result_ext_latency_ffs|
|xminute:2|lpm_add_sub:554|altshift:carry_ext_latency_ffs|
|xminute:2|lpm_add_sub:554|altshift:oflow_ext_latency_ffs|
|xhour:3|
|xhour:3|lpm_add_sub:180|
|xhour:3|lpm_add_sub:180|addcore:adder|
|xhour:3|lpm_add_sub:180|addcore:adder|addcore:adder0|
|xhour:3|lpm_add_sub:180|altshift:result_ext_latency_ffs|
|xhour:3|lpm_add_sub:180|altshift:carry_ext_latency_ffs|
|xhour:3|lpm_add_sub:180|altshift:oflow_ext_latency_ffs|
|xhour:3|lpm_add_sub:280|
|xhour:3|lpm_add_sub:280|addcore:adder|
|xhour:3|lpm_add_sub:280|addcore:adder|addcore:adder0|
|xhour:3|lpm_add_sub:280|altshift:result_ext_latency_ffs|
|xhour:3|lpm_add_sub:280|altshift:carry_ext_latency_ffs|
|xhour:3|lpm_add_sub:280|altshift:oflow_ext_latency_ffs|
|xalert:8|
|xsettime:9|
|xsettime:9|lpm_add_sub:170|
|xsettime:9|lpm_add_sub:170|addcore:adder|
|xsettime:9|lpm_add_sub:170|addcore:adder|addcore:adder0|
|xsettime:9|lpm_add_sub:170|altshift:result_ext_latency_ffs|
|xsettime:9|lpm_add_sub:170|altshift:carry_ext_latency_ffs|
|xsettime:9|lpm_add_sub:170|altshift:oflow_ext_latency_ffs|
|xdeled:10|
|74244:28|
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
***** Logic for device 'demo4' compiled without errors.
Device: EPM7128SLC84-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R
E E E E E E E E
S S S S V I I S S S S
L L L E E E E C R C O O E V E E E
A A A R R R R C E K _ _ R C R R R
M M M V G V V V I C S G D G D D V C V V V
P P P E N E E E N L E N S N S S E I E E E
2 1 0 D D D D D T K T D P D 2 1 D O D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
RESERVED | 12 74 | SETMIN
VCCIO | 13 73 | SETHOUR
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
RESERVED | 16 70 | G
RESERVED | 17 69 | F
RESERVED | 18 68 | E
GND | 19 67 | D
RESERVED | 20 66 | VCCIO
RESERVED | 21 65 | C
RESERVED | 22 EPM7128SLC84-6 64 | B
#TMS | 23 63 | A
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | SS2
VCCIO | 26 60 | SS1
RESERVED | 27 59 | GND
RESERVED | 28 58 | SS0
RESERVED | 29 57 | RESERVED
IO_DS7 | 30 56 | RESERVED
SPEAK | 31 55 | RESERVED
GND | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
S S S S S V S S S G V R R R G R R R R R V
W W W W W C W W W N C E E E N E E E E E C
1 2 3 4 5 C 6 7 8 D C S S S D S S S S S C
I I E E E E E E E E I
O N R R R R R R R R O
T V V V V V V V V
E E E E E E E E
D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 16/16(100%) 3/ 8( 37%) 9/16( 56%) 23/36( 63%)
B: LC17 - LC32 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 3/16( 18%) 3/ 8( 37%) 1/16( 6%) 8/36( 22%)
D: LC49 - LC64 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 3/16( 18%) 0/ 8( 0%) 0/16( 0%) 8/36( 22%)
F: LC81 - LC96 14/16( 87%) 4/ 8( 50%) 13/16( 81%) 25/36( 69%)
G: LC97 - LC112 8/16( 50%) 8/ 8(100%) 3/16( 18%) 5/36( 13%)
H: LC113 - LC128 16/16(100%) 4/ 8( 50%) 0/16( 0%) 14/36( 38%)
Total dedicated input pins used: 3/4 ( 75%)
Total I/O pins used: 31/64 ( 48%)
Total logic cells used: 60/128 ( 46%)
Total shareable expanders used: 21/128 ( 16%)
Total Turbo logic cells used: 60/128 ( 46%)
Total shareable expanders not available (n/a): 5/128 ( 3%)
Average fan-in: 6.00
Total fan-in: 360
Total input pins required: 13
Total fast input logic cells required: 0
Total output pins required: 17
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 60
Total flipflops required: 30
Total product terms required: 171
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 20
Synthesized logic cells: 7/ 128 ( 5%)
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo4\demo4.rpt
demo4
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 CKDSP
2 - - INPUT G 0 0 0 0 0 0 0 CLK
1 - - INPUT G 0 0 0 0 0 7 10 RESET
73 (115) (H) INPUT 0 0 0 0 0 0 1 SETHOUR
74 (117) (H) INPUT 0 0 0 0 0 0 1 SETMIN
33 (64) (D) INPUT 0 0 0 0 0 0 0 SW1
34 (61) (D) INPUT 0 0 0 0 0 0 0 SW2
35 (59) (D) INPUT 0 0 0 0 0 0 0 SW3
36 (57) (D) INPUT 0 0 0 0 0 0 0 SW4
37 (56) (D) INPUT 0 0 0 0 0 0 0 SW5
39 (53) (D) INPUT 0 0 0 0 0 0 0 SW6
40 (51) (D) INPUT 0 0 0 0 0 0 0 SW7
41 (49) (D) INPUT 0 0 0 0 0 0 0 SW8
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