xsettime.vhd

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library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity xsettime is
    port (
        hour: in STD_LOGIC_VECTOR (5 downto 0);
        min: in STD_LOGIC_VECTOR (6 downto 0);
        sec: in STD_LOGIC_VECTOR (6 downto 0);
        reset: in STD_LOGIC;
        clk: in STD_LOGIC;
        sel: out STD_LOGIC_VECTOR (2 downto 0);
        d_out: out STD_LOGIC_VECTOR (3 downto 0)
    );
end xsettime;

architecture xsettime_arch of xsettime is
signal sel1 : std_logic_vector(2 downto 0);
begin
  -- <<enter your statements here>>
process(clk,reset,sel1,hour,min,sec)
begin
if reset='0' then
  sel<="000";
  d_out<="0000";
  sel1<="000";
else
  if (clk='1' and clk'event) then
    if sel1<5 then
      sel1<=sel1+1;
    else
      sel1<="000";
    end if;
  end if;   
  sel<=sel1; 
  case sel1 is
    when "000" =>
      d_out(3)<='0';
      d_out(2)<='0';
      d_out(1)<=hour(5);
      d_out(0)<=hour(4);
    when "001" =>
      d_out<=hour(3 downto 0);
    when "010" =>
      d_out(3)<='0';
      d_out(2)<=min(6);
      d_out(1)<=min(5);
      d_out(0)<=min(4);
    when "011" =>
      d_out<=min(3 downto 0);
    when "100" =>
      d_out(3)<='0';
      d_out(2)<=sec(6);
      d_out(1)<=sec(5);
      d_out(0)<=sec(4);
    when "101" =>
      d_out<=sec(3 downto 0);
    when others =>
      null;
    end case;
end if;
end process;
end xsettime_arch;