xalert.vhd

DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity xalert is
    port (
        clk: in STD_LOGIC;
        d_in: in STD_LOGIC_VECTOR (6 downto 0);
        speak: out STD_LOGIC;
        d_out: out STD_LOGIC_VECTOR (2 downto 0)
    );
end xalert;

architecture xalert_arch of xalert is
type state is (s1,s2,s3,s4);
signal next_state,current_state : state;
begin
  -- <<enter your statements here>>

process(clk,current_state,d_in)
begin
if d_in/="0000000" then
  speak<='0';
  next_state<=s1;
  current_state<=s1;
  d_out<="000";
else
  if clk='1' and clk'event then
   speak<='1';
   current_state<=next_state;
  end if;
  case current_state is
   when s1 =>
     d_out<="000";
     next_state<=s2;
   when s2 =>
     d_out<="001";
     next_state<=s3;
   when s3 =>
     d_out<="010";
     next_state<=s4;
   when s4 =>
     d_out<="100";
     next_state<=s1;
   when others =>
     d_out<="000";
     null;
   end case;
end if;
end process;
end xalert_arch;