xlcd2.vhd

DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计

library IEEE;
use IEEE.std_logic_1164.all;

entity xlcd2 is
    port (
        clk: in STD_LOGIC;
        reset: in STD_LOGIC;
        enda: in STD_LOGIC;
        clkout: out STD_LOGIC;
        mrdn: out STD_LOGIC;
        lwrn: out STD_LOGIC
    );
end xlcd2;

architecture xlcd2_arch of xlcd2 is
type state is (s1,s2,s3,s4);
attribute ENUM_ENCODING: string;
attribute ENUM_ENCODING of state: type is "00 01 10 11";
signal current_state,next_state : state;
begin
  -- <<enter your statements here>>

process(reset,current_state,enda)
begin
if reset='0' then
   next_state<=s2;
   mrdn<='1';
   clkout<='1';
   if enda='0' then
    lwrn<='1';
   else
    lwrn<='0';
   end if;
else
   case current_state is
      when s1 =>
				mrdn<='0';
				lwrn<='1';
				clkout<='1';
                next_state<=s2;
      when s2 =>
				mrdn<='0';
				lwrn<='0';
				clkout<='0';
                next_state<=s3;
      when s3 =>
				mrdn<='0';
				lwrn<='1';
				clkout<='0';
                next_state<=s4;
      when s4 =>
				mrdn<='1';
				lwrn<='1';
				clkout<='1';
                next_state<=s1;
      when others =>
                next_state<=s1;
                mrdn<='0';
                lwrn<='0';
                clkout<='1';
   end case;
end if;
end process; 

process(clk)
begin
if (clk='1' and clk'event) then
 current_state<=next_state;
end if;
end process;

end xlcd2_arch;