xlcd1.vhd

DEMO2 数码管扫描显示电路/DEMO4 计数时钟 DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity xlcd1 is
    port (
        clk: in STD_LOGIC;
        reset: in STD_LOGIC;
        cd: out STD_LOGIC;
        mema: out STD_LOGIC_VECTOR(9 downto 0);
        enda: out STD_LOGIC
         );
end xlcd1;

architecture xlcd1_arch of xlcd1 is
signal temp : std_logic_vector(13 downto 0);
signal to2k : std_logic;
begin
-- <<enter your statements here>>

process(clk,reset)
begin
if reset='0' then
   temp<="00000000000000";
   cd<='0';
   to2k<='0';
   enda<='0';
else
  if (clk='1' and clk'event) then
  if to2k='0' then 
     if temp>=8211 then
        to2k<='1';
        temp<="00000000010011";
--        cd<='1';
     else
        to2k<='0';
        if temp<=18 then
           mema<=temp(9 downto 0);
        else
           mema<="0000000000";
        end if;
        if (temp=2 or temp=5 or temp=8 or temp=11 or temp=12 
              or temp=13 or temp=14 or temp=17 or temp=18) then
                  cd<='1';
        else
                  cd<='0';
        end if;
        temp<=temp+1;
     end if;
  else
      to2k<='1';
      mema<=temp(9 downto 0);
      if (temp=19 or temp=22 or temp=23 or temp=536) then
                   cd<='1';
      else
                   cd<='0';
      end if;     
      if temp<=536 then
         temp<=temp+1;
      else
         enda<='1'; 
         temp<="00001000011001";
      end if;        
  end if;
  end if;
end if;
end process;

end xlcd1_arch;