📄 demo9.rpt
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Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo9\demo9.rpt
demo9
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 10/16( 62%) 1/ 8( 12%) 14/16( 87%) 29/36( 80%)
D: LC49 - LC64 16/16(100%) 8/ 8(100%) 16/16(100%) 31/36( 86%)
E: LC65 - LC80 16/16(100%) 8/ 8(100%) 14/16( 87%) 26/36( 72%)
F: LC81 - LC96 16/16(100%) 1/ 8( 12%) 16/16(100%) 26/36( 72%)
G: LC97 - LC112 14/16( 87%) 8/ 8(100%) 16/16(100%) 32/36( 88%)
H: LC113 - LC128 16/16(100%) 8/ 8(100%) 16/16(100%) 28/36( 77%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 35/64 ( 54%)
Total logic cells used: 88/128 ( 68%)
Total shareable expanders used: 59/128 ( 46%)
Total Turbo logic cells used: 88/128 ( 68%)
Total shareable expanders not available (n/a): 33/128 ( 25%)
Average fan-in: 11.23
Total fan-in: 989
Total input pins required: 18
Total fast input logic cells required: 0
Total output pins required: 15
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 88
Total flipflops required: 29
Total product terms required: 346
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 51
Synthesized logic cells: 33/ 128 ( 25%)
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo9\demo9.rpt
demo9
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 CLK
44 (65) (E) INPUT 0 0 0 0 0 0 0 D0
45 (67) (E) INPUT 0 0 0 0 0 0 0 D1
46 (69) (E) INPUT 0 0 0 0 0 0 0 D2
48 (72) (E) INPUT 0 0 0 0 0 0 0 D3
49 (73) (E) INPUT 0 0 0 0 0 0 0 D4
50 (75) (E) INPUT 0 0 0 0 0 0 0 D5
51 (77) (E) INPUT 0 0 0 0 0 0 0 D6
52 (80) (E) INPUT 0 0 0 0 0 0 0 D7
1 - - INPUT G 0 0 0 0 0 9 12 RESET
33 (64) (D) INPUT 0 0 0 0 0 0 0 SW1
34 (61) (D) INPUT 0 0 0 0 0 0 0 SW2
35 (59) (D) INPUT 0 0 0 0 0 0 0 SW3
36 (57) (D) INPUT 0 0 0 0 0 0 0 SW4
37 (56) (D) INPUT 0 0 0 0 0 0 0 SW5
39 (53) (D) INPUT 0 0 0 0 0 0 0 SW6
40 (51) (D) INPUT 0 0 0 0 0 0 0 SW7
41 (49) (D) INPUT 0 0 0 0 0 0 0 SW8
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo9\demo9.rpt
demo9
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
76 120 H OUTPUT t 0 0 0 0 1 0 0 CD
80 126 H OUTPUT t 0 0 0 0 0 0 0 IO_DS1
81 128 H OUTPUT t 0 0 0 0 0 0 0 IO_DS2
79 125 H OUTPUT t 0 0 0 1 3 0 0 LWRM
63 97 G OUTPUT t 0 0 0 0 1 0 1 MEMA0
64 99 G OUTPUT t 0 0 0 0 1 0 1 MEMA1
65 101 G FF t 5 3 0 1 18 1 1 MEMA2
67 104 G FF t 5 3 0 1 18 1 1 MEMA3
68 105 G FF t 2 2 0 1 17 0 1 MEMA4
69 107 G OUTPUT t 0 0 0 0 1 0 0 MEMA5
70 109 G FF t 5 1 1 1 17 1 0 MEMA6
73 115 H FF t 5 1 1 1 17 1 0 MEMA7
74 117 H FF t 5 1 1 1 17 1 0 MEMA8
75 118 H FF t 5 1 1 1 17 1 0 MEMA9
77 123 H OUTPUT t 0 0 0 1 2 0 0 MRON
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo9\demo9.rpt
demo9
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 106 G SOFT t 0 0 0 0 2 0 1 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder0|result_node1
- 54 D SOFT t 0 0 0 0 3 0 2 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder0|result_node2
- 114 H SOFT t 0 0 0 0 4 0 2 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder0|result_node3
(34) 61 D SOFT t 0 0 0 0 5 0 2 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder0|result_node4
- 79 E SOFT t 0 0 0 0 6 0 2 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder0|result_node5
- 78 E SOFT t 0 0 0 0 7 0 2 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder0|result_node6
(52) 80 E SOFT t 0 0 0 0 8 0 2 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder0|result_node7
(46) 69 E SOFT t 0 0 0 0 9 0 2 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder1|result_node0
- 95 F SOFT t 0 0 0 0 12 0 2 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder1|result_node3
(55) 85 F SOFT t 0 0 0 0 13 0 2 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder1|result_node4
- 87 F SOFT t 0 0 0 0 14 0 2 |XLCD1:1|LPM_ADD_SUB:1062|addcore:adder|addcore:adder1|result_node5
- 108 G SOFT t 0 0 0 0 2 0 1 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder0|result_node1
(39) 53 D SOFT t 0 0 0 0 3 0 2 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder0|result_node2
- 116 H SOFT t 0 0 0 0 4 0 2 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder0|result_node3
- 68 E SOFT t 0 0 0 0 5 0 2 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder0|result_node4
- 71 E SOFT t 0 0 0 0 6 0 2 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder0|result_node5
(49) 73 E SOFT t 0 0 0 0 7 0 2 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder0|result_node6
(48) 72 E SOFT t 0 0 0 0 8 0 2 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder0|result_node7
- 66 E SOFT t 0 0 0 0 9 0 2 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder1|result_node0
- 92 F SOFT t 0 0 0 0 12 0 2 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder1|result_node3
(62) 96 F SOFT t 0 0 0 0 13 0 2 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder1|result_node4
- 90 F SOFT t 0 0 0 0 14 0 2 |XLCD1:1|LPM_ADD_SUB:1695|addcore:adder|addcore:adder1|result_node5
(54) 83 F DFFE s t r 4 0 1 0 22 1 1 |XLCD1:1|~3~fit~in1
- 89 F DFFE s t r 5 1 1 1 17 1 1 |XLCD1:1|~13~fit~in1
- 41 C DFFE s t r 6 3 0 1 18 1 1 |XLCD1:1|~21~fit~in1
- 74 E DFFE s t r 6 3 0 1 18 1 1 |XLCD1:1|~23~fit~in1
(45) 67 E DFFE t 2 0 1 0 17 1 1 |XLCD1:1|:25
- 58 D DFFE t 3 0 0 0 15 7 45 |XLCD1:1|temp13 (|XLCD1:1|:27)
(36) 57 D DFFE t 3 0 0 0 15 7 41 |XLCD1:1|temp12 (|XLCD1:1|:28)
(37) 56 D DFFE t 3 0 0 0 15 7 44 |XLCD1:1|temp11 (|XLCD1:1|:29)
- 84 F TFFE t 1 0 1 0 14 7 45 |XLCD1:1|temp10 (|XLCD1:1|:30)
- 81 F DFFE t 2 0 1 0 16 7 47 |XLCD1:1|temp9 (|XLCD1:1|:31)
- 33 C DFFE t 0 0 0 0 3 7 47 |XLCD1:1|temp8 (|XLCD1:1|:32)
(51) 77 E DFFE t 3 0 0 0 15 7 49 |XLCD1:1|temp7 (|XLCD1:1|:33)
- 110 G DFFE t 0 0 0 0 3 7 51 |XLCD1:1|temp6 (|XLCD1:1|:34)
- 42 C DFFE t 0 0 0 0 3 7 53 |XLCD1:1|temp5 (|XLCD1:1|:35)
- 119 H DFFE t 1 0 1 0 18 6 55 |XLCD1:1|temp4 (|XLCD1:1|:36)
- 100 G DFFE t 0 0 0 0 4 7 49 |XLCD1:1|temp3 (|XLCD1:1|:37)
(25) 45 C DFFE t 0 0 0 0 3 7 48 |XLCD1:1|temp2 (|XLCD1:1|:38)
(28) 40 C DFFE t 4 0 1 0 18 7 50 |XLCD1:1|temp1 (|XLCD1:1|:39)
- 113 H DFFE t 1 0 1 0 17 7 51 |XLCD1:1|temp0 (|XLCD1:1|:40)
(60) 93 F DFFE t 1 0 1 0 16 7 43 |XLCD1:1|to2k (|XLCD1:1|:41)
(57) 88 F SOFT s t 1 0 1 1 15 1 0 |XLCD1:1|~1922~1
- 103 G SOFT s t 0 0 0 1 4 1 0 |XLCD1:1|~1922~2
- 102 G SOFT s t 1 0 1 1 13 1 0 |XLCD1:1|~1928~1
- 98 G SOFT s t 1 0 1 1 13 1 0 |XLCD1:1|~1934~1
(56) 86 F SOFT s t 1 0 1 1 16 0 1 |XLCD1:1|~1940~1
- 70 E SOFT s t 1 0 1 1 16 0 1 |XLCD1:1|~1946~1
- 82 F SOFT s t 1 0 1 0 15 0 1 |XLCD1:1|~1952~1
- 34 C SOFT s t 1 0 1 0 8 0 1 |XLCD1:1|~1952~2
- 63 D SOFT s t 1 0 1 0 8 0 1 |XLCD1:1|~1952~3
(29) 38 C SOFT s t 1 0 1 0 7 0 1 |XLCD1:1|~1952~4
(31) 35 C SOFT s t 1 0 1 0 6 0 1 |XLCD1:1|~1952~5
- 52 D SOFT s t 1 0 1 0 17 0 1 |XLCD1:1|~1964~1
(40) 51 D SOFT s t 1 0 1 0 17 0 1 |XLCD1:1|~1970~1
- 50 D SOFT s t 1 0 1 0 17 0 1 |XLCD1:1|~1976~1
(44) 65 E SOFT s t 1 0 1 0 17 0 1 |XLCD1:1|~1994~1
- 76 E SOFT s t 0 0 0 0 13 0 1 |XLCD1:1|~1994~2
(50) 75 E SOFT s t 1 0 1 0 17 0 1 |XLCD1:1|~2000~1
(33) 64 D SOFT s t 1 0 1 0 17 0 1 |XLCD1:1|~2006~1
- 60 D SOFT s t 0 0 0 0 13 0 1 |XLCD1:1|~2006~2
- 44 C SOFT s t 1 0 1 0 17 0 1 |XLCD1:1|~2012~1
(27) 43 C SOFT s t 0 0 0 0 13 0 1 |XLCD1:1|~2012~2
- 121 H SOFT s t 1 0 1 0 14 0 1 |XLCD1:1|~2018~1
(35) 59 D SOFT s t 1 0 1 0 17 0 1 |XLCD1:1|~2024~1
- 62 D SOFT s t 0 0 0 0 13 0 1 |XLCD1:1|~2024~2
(41) 49 D SOFT s t 1 0 1 0 17 0 1 |XLCD1:1|~2030~1
- 55 D SOFT s t 0 0 0 0 13 0 1 |XLCD1:1|~2030~2
(61) 94 F SOFT s t 0 0 0 0 16 0 1 |XLCD1:1|~2036~1
(58) 91 F SOFT s t 0 0 0 0 12 0 1 |XLCD1:1|~2042~1
- 127 H DFFE + t 0 0 0 1 2 2 2 |XLCD2:3|current_state1 (|XLCD2:3|:9)
- 122 H DFFE + t 0 0 0 1 1 2 3 |XLCD2:3|current_state0 (|XLCD2:3|:10)
- 124 H SOFT s t 0 0 0 1 2 7 20 |XLCD2:3|~221~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\eda-240h\altera\7128_84_vhdl\demo9\demo9.rpt
demo9
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
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