sdhprocess_tb.vhd

光纤通信中的SDH数据帧解析及提取的VHDL实现源代码

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--
-- Title       : Test Bench for sdhprocess
-- Design      : Project1
-- Author      : zhangxb
-- Company     : THU
--
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--
-- File        : $DSN\src\TestBench\sdhprocess_TB.vhd
-- Generated   : 2006-11-25, 21:50
-- From        : $DSN\src\Main.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
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--
-- Description : Automatically generated Test Bench for sdhprocess_tb
--
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library ieee;
use work.subblock.all;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity sdhprocess_tb is
end sdhprocess_tb;

architecture TB_ARCHITECTURE of sdhprocess_tb is
	-- Component declaration of the tested unit
	component sdhprocess
	port(
		clk_1944M : in std_logic;
		clk_10M : in std_logic;
		datain : in std_logic_vector(7 downto 0);
		E1Dataout : out std_logic;
		F1Dataout : out std_logic;
		clk_64K : inout std_logic;
		DCC1Dataout : out std_logic;
		clk_192K : inout std_logic;
		SDHHeadDataout : out std_logic );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal clk_1944M : std_logic := '0';
	signal clk_10M : std_logic := '0';
	signal datain : std_logic_vector(7 downto 0);
	signal clk_64K : std_logic;
	signal clk_192K : std_logic;
	-- Observed signals - signals mapped to the output ports of tested entity
	signal E1Dataout : std_logic;
	signal F1Dataout : std_logic;
	signal DCC1Dataout : std_logic;
	signal HeadSignal : std_logic;
	signal SDHHeadDataout : std_logic;

	-- Add your code here ...
--signal code: std_logic_vector(14 downto 0) := "111111111111111";
--signal randomvector: std_logic_vector(7 downto 0) := "00000000";
constant A1:std_logic_vector(7 downto 0) :="11110110";
constant A2:std_logic_vector(7 downto 0) :="00101000";
constant E1:std_logic_vector(7 downto 0) :="11100001";
constant F1:std_logic_vector(7 downto 0) :="11110001";
constant D1:std_logic_vector(7 downto 0) :="11110000";
constant D2:std_logic_vector(7 downto 0) :="00001111";
constant D3:std_logic_vector(7 downto 0) :="11001100";


begin
	-- Unit Under Test port map
	UUT : sdhprocess
		port map (
			clk_1944M => clk_1944M,
			clk_10M => clk_10M,
			datain => datain,
			E1Dataout => E1Dataout,
			F1Dataout => F1Dataout,
			clk_64K => clk_64K,
			DCC1Dataout => DCC1Dataout,
			clk_192K => clk_192K,
			SDHHeadDataout => SDHHeadDataout
		);

	-- Add your stimulus here ...
	clk_1944M <= not clk_1944M after 25.72 ns;
	clk_10M <= not clk_10M after 50 ns;

	
--生成帧数据
	Senddata : process(clk_1944M)
	variable count: integer :=0; 
	begin
		if clk_1944M = '1' then
			if count <= 2 then
				datain <= A1;
				count := count + 1;
			elsif count <= 5 then
				datain <= A2;
				count := count + 1;
			elsif count = 273 then
				datain <= E1;
				count := count + 1;
			elsif count = 276 then
				datain <= F1;
				count := count + 1;
			elsif count = 540 then
				datain <= D1;
				count := count + 1;
			elsif count = 543 then
				datain <= D2;
				count := count + 1;
			elsif count = 546 then
				datain <= D3;
				count := count + 1;
			else
				datain <= "00000000";
				count := count + 1;
			end if;
		end if;
		if count = 2430 then
			count := 0;
		end if;
	end process Senddata;
end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_sdhprocess of sdhprocess_tb is
	for TB_ARCHITECTURE
		for UUT : sdhprocess
			use entity work.sdhprocess(sdhprocess);
		end for;
	end for;
end TESTBENCH_FOR_sdhprocess;