display.vhd

来自「CPLD控制交通灯程序」· VHDL 代码 · 共 32 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY display IS
	PORT
	(
		clock : IN STD_LOGIC;		--clock is 4MHZ
		qin : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		display : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END display;
ARCHITECTURE light OF display IS
BEGIN
	PROCESS (clock)
	BEGIN
		IF rising_edge(clock) THEN
			CASE qin IS
				WHEN "0000" => display <="1000000";
    			WHEN "0001" => display <="1111001";
				WHEN "0010" => display <="0100100";
				WHEN "0011" => display <="0110000";
				WHEN "0100" => display <="0011001";
				WHEN "0101" => display <="0010010";
				WHEN "0110" => display <="0000010";
				WHEN "0111" => display <="1111000";
				WHEN "1000" => display <="0000000";
				WHEN "1001" => display <="0010000";
				WHEN OTHERS => display <="1111111";
			END CASE;
		END IF;
	END PROCESS;
END light;