fenei.vhd

来自「CPLD控制交通灯程序」· VHDL 代码 · 共 30 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY fenei IS
	PORT
	(
		clock : IN STD_LOGIC;
		numin : IN INTEGER RANGE 0 TO 25;
		numa,numb : OUT INTEGER RANGE 0 TO 9
	);
END fenei;

ARCHITECTURE a OF fenei IS
BEGIN
	PROCESS (clock)
	BEGIN
		IF rising_edge(clock) THEN
			IF numin >= 20 THEN
				numa <= 2;
				numb <= numin-20;
			ELSIF numin >= 10 THEN
				numa <= 1;
				numb <= numin-10;	
			ELSE
				numa <= 0;
				numb <= numin;
			END IF;
		END IF;
	END PROCESS;
END a;