frequency.tan.qmsg

CPLD控制交通灯程序

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk4m 12 " "Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock \"clk4m\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "74390:3\|32 74390:3\|32 clk4m 4.0 ns " "Info: Found hold time violation between source  pin or register \"74390:3\|32\" and destination pin or register \"74390:3\|32\" for clock \"clk4m\" (Hold time is 4.0 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "9.000 ns + Largest " "Info: + Largest clock skew is 9.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4m destination 137.000 ns + Longest register " "Info: + Longest clock path from clock \"clk4m\" to destination register is 137.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk4m 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk4m'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clk4m } "NODE_NAME" } "" } } { "frequency.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/frequency.bdf" { { 168 96 264 184 "clk4m" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns 74390:1\|7 2 REG LC1 3 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1; Fanout = 3; REG Node = '74390:1\|7'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "1.000 ns" { clk4m 74390:1|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns 74390:1\|3 3 REG LC5 3 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC5; Fanout = 3; REG Node = '74390:1\|3'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:1|7 74390:1|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns 74390:1\|34 4 REG LC6 3 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC6; Fanout = 3; REG Node = '74390:1\|34'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:1|3 74390:1|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 31.000 ns 74390:1\|31 5 REG LC9 3 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC9; Fanout = 3; REG Node = '74390:1\|31'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:1|34 74390:1|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 40.000 ns 74390:2\|7 6 REG LC10 3 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC10; Fanout = 3; REG Node = '74390:2\|7'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:1|31 74390:2|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 49.000 ns 74390:2\|3 7 REG LC13 3 " "Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 49.000 ns; Loc. = LC13; Fanout = 3; REG Node = '74390:2\|3'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:2|7 74390:2|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 58.000 ns 74390:2\|34 8 REG LC14 3 " "Info: 8: + IC(2.000 ns) + CELL(7.000 ns) = 58.000 ns; Loc. = LC14; Fanout = 3; REG Node = '74390:2\|34'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:2|3 74390:2|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 67.000 ns 5 9 REG LC15 3 " "Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 67.000 ns; Loc. = LC15; Fanout = 3; REG Node = '5'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:2|34 5 } "NODE_NAME" } "" } } { "frequency.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/frequency.bdf" { { 24 1008 1072 104 "5" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 76.000 ns 74390:2\|31 10 REG LC19 3 " "Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 76.000 ns; Loc. = LC19; Fanout = 3; REG Node = '74390:2\|31'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 5 74390:2|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 85.000 ns 74390:3\|7 11 REG LC20 3 " "Info: 11: + IC(2.000 ns) + CELL(7.000 ns) = 85.000 ns; Loc. = LC20; Fanout = 3; REG Node = '74390:3\|7'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:2|31 74390:3|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 94.000 ns 74390:3\|3 12 REG LC23 3 " "Info: 12: + IC(2.000 ns) + CELL(7.000 ns) = 94.000 ns; Loc. = LC23; Fanout = 3; REG Node = '74390:3\|3'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:3|7 74390:3|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 103.000 ns 74390:3\|34 13 REG LC24 3 " "Info: 13: + IC(2.000 ns) + CELL(7.000 ns) = 103.000 ns; Loc. = LC24; Fanout = 3; REG Node = '74390:3\|34'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:3|3 74390:3|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 112.000 ns 74390:3\|31 14 REG LC17 3 " "Info: 14: + IC(2.000 ns) + CELL(7.000 ns) = 112.000 ns; Loc. = LC17; Fanout = 3; REG Node = '74390:3\|31'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:3|34 74390:3|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(8.000 ns) 122.000 ns 74390:3\|29~7 15 COMB SEXP17 1 " "Info: 15: + IC(2.000 ns) + CELL(8.000 ns) = 122.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '74390:3\|29~7'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "10.000 ns" { 74390:3|31 74390:3|29~7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 904 408 472 944 "29" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.000 ns) 129.000 ns 74390:3\|33 16 REG LC25 3 " "Info: 16: + IC(0.000 ns) + CELL(7.000 ns) = 129.000 ns; Loc. = LC25; Fanout = 3; REG Node = '74390:3\|33'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "7.000 ns" { 74390:3|29~7 74390:3|33 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 137.000 ns 74390:3\|32 17 REG LC26 2 " "Info: 17: + IC(2.000 ns) + CELL(6.000 ns) = 137.000 ns; Loc. = LC26; Fanout = 2; REG Node = '74390:3\|32'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { 74390:3|33 74390:3|32 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 760 520 584 840 "32" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "109.000 ns ( 79.56 % ) " "Info: Total cell delay = 109.000 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "28.000 ns ( 20.44 % ) " "Info: Total interconnect delay = 28.000 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "137.000 ns" { clk4m 74390:1|7 74390:1|3 74390:1|34 74390:1|31 74390:2|7 74390:2|3 74390:2|34 5 74390:2|31 74390:3|7 74390:3|3 74390:3|34 74390:3|31 74390:3|29~7 74390:3|33 74390:3|32 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "137.000 ns" { clk4m clk4m~out 74390:1|7 74390:1|3 74390:1|34 74390:1|31 74390:2|7 74390:2|3 74390:2|34 5 74390:2|31 74390:3|7 74390:3|3 74390:3|34 74390:3|31 74390:3|29~7 74390:3|33 74390:3|32 } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 8.000ns 7.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4m source 128.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk4m\" to source register is 128.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk4m 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk4m'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clk4m } "NODE_NAME" } "" } } { "frequency.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/frequency.bdf" { { 168 96 264 184 "clk4m" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns 74390:1\|7 2 REG LC1 3 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1; Fanout = 3; REG Node = '74390:1\|7'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "1.000 ns" { clk4m 74390:1|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns 74390:1\|3 3 REG LC5 3 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC5; Fanout = 3; REG Node = '74390:1\|3'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:1|7 74390:1|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns 74390:1\|34 4 REG LC6 3 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC6; Fanout = 3; REG Node = '74390:1\|34'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/frequency.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { 74390:1|3 74390:1|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/a