leddongtai.tan.qmsg

CPLD控制交通灯程序

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register count\[0\] register leddisp\[2\]~reg0 76.92 MHz 13.0 ns Internal " "Info: Clock \"clock\" has Internal fmax of 76.92 MHz between source register \"count\[0\]\" and destination register \"leddisp\[2\]~reg0\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LC1 35 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 35; REG Node = 'count\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { count[0] } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns leddisp\[2\]~reg0 2 REG LC17 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'leddisp\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { count[0] leddisp[2]~reg0 } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { count[0] leddisp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { count[0] leddisp[2]~reg0 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns leddisp\[2\]~reg0 2 REG LC17 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'leddisp\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock leddisp[2]~reg0 } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock leddisp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out leddisp[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns count\[0\] 2 REG LC1 35 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 35; REG Node = 'count\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock count[0] } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock leddisp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out leddisp[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { count[0] leddisp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { count[0] leddisp[2]~reg0 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock leddisp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out leddisp[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock count[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out count[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "leddisp\[2\]~reg0 snl\[2\] clock 11.000 ns register " "Info: tsu for register \"leddisp\[2\]~reg0\" (data pin = \"snl\[2\]\", clock pin = \"clock\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns snl\[2\] 1 PIN PIN_50 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_50; Fanout = 1; PIN Node = 'snl\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { snl[2] } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns leddisp\[2\]~reg0 2 REG LC17 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'leddisp\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { snl[2] leddisp[2]~reg0 } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "10.000 ns" { snl[2] leddisp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { snl[2] snl[2]~out leddisp[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns leddisp\[2\]~reg0 2 REG LC17 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'leddisp\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock leddisp[2]~reg0 } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock leddisp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out leddisp[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "10.000 ns" { snl[2] leddisp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { snl[2] snl[2]~out leddisp[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock leddisp[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out leddisp[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock leddisp\[6\] leddisp\[6\]~reg0 8.000 ns register " "Info: tco from clock \"clock\" to destination pin \"leddisp\[6\]\" through register \"leddisp\[6\]~reg0\" is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 14 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns leddisp\[6\]~reg0 2 REG LC21 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC21; Fanout = 1; REG Node = 'leddisp\[6\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock leddisp[6]~reg0 } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock leddisp[6]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out leddisp[6]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns leddisp\[6\]~reg0 1 REG LC21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 1; REG Node = 'leddisp\[6\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { leddisp[6]~reg0 } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns leddisp\[6\] 2 PIN PIN_20 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'leddisp\[6\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "4.000 ns" { leddisp[6]~reg0 leddisp[6] } "NODE_NAME" } "" } } { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 100.00 % ) " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "4.000 ns" { leddisp[6]~reg0 leddisp[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { leddisp[6]~reg0 leddisp[6] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock leddisp[6]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out leddisp[6]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "leddongtai" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/leddongtai.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "4.000 ns" { leddisp[6]~reg0 leddisp[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { leddisp[6]~reg0 leddisp[6] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}