controller.tan.qmsg

CPLD控制交通灯程序

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register countnum\[1\] register numb\[2\]~reg0 66.67 MHz 15.0 ns Internal " "Info: Clock \"clock\" has Internal fmax of 66.67 MHz between source register \"countnum\[1\]\" and destination register \"numb\[2\]~reg0\" (period= 15.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest register register " "Info: + Longest register to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns countnum\[1\] 1 REG LC9 60 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC9; Fanout = 60; REG Node = 'countnum\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { countnum[1] } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns numb~1983 2 COMB LC22 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC22; Fanout = 1; COMB Node = 'numb~1983'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { countnum[1] numb~1983 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns numb~1985 3 COMB LC23 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC23; Fanout = 1; COMB Node = 'numb~1985'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "1.000 ns" { numb~1983 numb~1985 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 10.000 ns numb\[2\]~reg0 4 REG LC24 1 " "Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC24; Fanout = 1; REG Node = 'numb\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "1.000 ns" { numb~1985 numb[2]~reg0 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "10.000 ns" { countnum[1] numb~1983 numb~1985 numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { countnum[1] numb~1983 numb~1985 numb[2]~reg0 } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 23 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 23; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns numb\[2\]~reg0 2 REG LC24 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC24; Fanout = 1; REG Node = 'numb\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock numb[2]~reg0 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numb[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 23 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 23; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns countnum\[1\] 2 REG LC9 60 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC9; Fanout = 60; REG Node = 'countnum\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock countnum[1] } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock countnum[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out countnum[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numb[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock countnum[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out countnum[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "10.000 ns" { countnum[1] numb~1983 numb~1985 numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { countnum[1] numb~1983 numb~1985 numb[2]~reg0 } { 0.000ns 2.000ns 0.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 1.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numb[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock countnum[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out countnum[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "greenb~reg0 hold clock 12.000 ns register " "Info: tsu for register \"greenb~reg0\" (data pin = \"hold\", clock pin = \"clock\") is 12.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest pin register " "Info: + Longest pin to register delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns hold 1 PIN PIN_81 31 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 31; PIN Node = 'hold'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { hold } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns greenb~47 2 COMB LC18 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC18; Fanout = 1; COMB Node = 'greenb~47'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { hold greenb~47 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 11.000 ns greenb~reg0 3 REG LC19 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC19; Fanout = 1; REG Node = 'greenb~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "1.000 ns" { greenb~47 greenb~reg0 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 81.82 % ) " "Info: Total cell delay = 9.000 ns ( 81.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 18.18 % ) " "Info: Total interconnect delay = 2.000 ns ( 18.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "11.000 ns" { hold greenb~47 greenb~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.000 ns" { hold hold~out greenb~47 greenb~reg0 } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 23 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 23; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns greenb~reg0 2 REG LC19 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC19; Fanout = 1; REG Node = 'greenb~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock greenb~reg0 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock greenb~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out greenb~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "11.000 ns" { hold greenb~47 greenb~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "11.000 ns" { hold hold~out greenb~47 greenb~reg0 } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 6.000ns 1.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock greenb~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out greenb~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock numa\[4\] numa\[4\]~reg0 8.000 ns register " "Info: tco from clock \"clock\" to destination pin \"numa\[4\]\" through register \"numa\[4\]~reg0\" is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 23 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 23; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns numa\[4\]~reg0 2 REG LC21 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC21; Fanout = 1; REG Node = 'numa\[4\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock numa[4]~reg0 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numa[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numa[4]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns numa\[4\]~reg0 1 REG LC21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 1; REG Node = 'numa\[4\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { numa[4]~reg0 } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns numa\[4\] 2 PIN PIN_20 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'numa\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "4.000 ns" { numa[4]~reg0 numa[4] } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 100.00 % ) " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "4.000 ns" { numa[4]~reg0 numa[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { numa[4]~reg0 numa[4] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numa[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numa[4]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "controller" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/controller.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "4.000 ns" { numa[4]~reg0 numa[4] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { numa[4]~reg0 numa[4] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}