📄 traffic_light.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk4m " "Info: Assuming node \"clk4m\" is an undefined clock" { } { { "traffic_light.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/traffic_light.bdf" { { 0 520 688 16 "clk4m" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk4m" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "26 " "Warning: Found 26 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|5 " "Info: Detected ripple clock \"frequency:inst4\|5\" as buffer" { } { { "frequency.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/frequency.bdf" { { 24 1008 1072 104 "5" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|5" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "frequency:inst4\|74390:2\|29~7 " "Info: Detected gated clock \"frequency:inst4\|74390:2\|29~7\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 904 408 472 944 "29" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:2\|29~7" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:2\|33 " "Info: Detected ripple clock \"frequency:inst4\|74390:2\|33\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:2\|33" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:2\|31 " "Info: Detected ripple clock \"frequency:inst4\|74390:2\|31\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:2\|31" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:3\|7 " "Info: Detected ripple clock \"frequency:inst4\|74390:3\|7\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:3\|7" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "frequency:inst4\|74390:3\|20~7 " "Info: Detected gated clock \"frequency:inst4\|74390:3\|20~7\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 344 408 472 384 "20" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:3\|20~7" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:3\|6 " "Info: Detected ripple clock \"frequency:inst4\|74390:3\|6\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 328 520 584 408 "6" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:3\|6" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:3\|3 " "Info: Detected ripple clock \"frequency:inst4\|74390:3\|3\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:3\|3" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:3\|34 " "Info: Detected ripple clock \"frequency:inst4\|74390:3\|34\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:3\|34" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "frequency:inst4\|74390:3\|29~7 " "Info: Detected gated clock \"frequency:inst4\|74390:3\|29~7\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 904 408 472 944 "29" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:3\|29~7" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:3\|33 " "Info: Detected ripple clock \"frequency:inst4\|74390:3\|33\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:3\|33" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:3\|31 " "Info: Detected ripple clock \"frequency:inst4\|74390:3\|31\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:3\|31" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|4 " "Info: Detected ripple clock \"frequency:inst4\|4\" as buffer" { } { { "frequency.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/frequency.bdf" { { 24 904 968 104 "4" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|4" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:2\|34 " "Info: Detected ripple clock \"frequency:inst4\|74390:2\|34\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:2\|34" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:2\|3 " "Info: Detected ripple clock \"frequency:inst4\|74390:2\|3\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:2\|3" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "frequency:inst4\|74390:2\|20~7 " "Info: Detected gated clock \"frequency:inst4\|74390:2\|20~7\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 344 408 472 384 "20" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:2\|20~7" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:2\|6 " "Info: Detected ripple clock \"frequency:inst4\|74390:2\|6\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 328 520 584 408 "6" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:2\|6" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:2\|7 " "Info: Detected ripple clock \"frequency:inst4\|74390:2\|7\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:2\|7" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:1\|31 " "Info: Detected ripple clock \"frequency:inst4\|74390:1\|31\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:1\|31" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "frequency:inst4\|74390:1\|29~7 " "Info: Detected gated clock \"frequency:inst4\|74390:1\|29~7\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 904 408 472 944 "29" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:1\|29~7" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:1\|33 " "Info: Detected ripple clock \"frequency:inst4\|74390:1\|33\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:1\|33" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:1\|34 " "Info: Detected ripple clock \"frequency:inst4\|74390:1\|34\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:1\|34" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:1\|3 " "Info: Detected ripple clock \"frequency:inst4\|74390:1\|3\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:1\|3" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "frequency:inst4\|74390:1\|20~7 " "Info: Detected gated clock \"frequency:inst4\|74390:1\|20~7\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 344 408 472 384 "20" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:1\|20~7" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:1\|6 " "Info: Detected ripple clock \"frequency:inst4\|74390:1\|6\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 328 520 584 408 "6" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:1\|6" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "frequency:inst4\|74390:1\|7 " "Info: Detected ripple clock \"frequency:inst4\|74390:1\|7\" as buffer" { } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "frequency:inst4\|74390:1\|7" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk4m register controller:inst\|numb\[1\] register fenei:inst8\|numb\[3\] 17.24 MHz 58.0 ns Internal " "Info: Clock \"clk4m\" has Internal fmax of 17.24 MHz between source register \"controller:inst\|numb\[1\]\" and destination register \"fenei:inst8\|numb\[3\]\" (period= 58.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns controller:inst\|numb\[1\] 1 REG LC36 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC36; Fanout = 8; REG Node = 'controller:inst\|numb\[1\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { controller:inst|numb[1] } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns fenei:inst8\|numb\[3\] 2 REG LC44 17 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC44; Fanout = 17; REG Node = 'fenei:inst8\|numb\[3\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { controller:inst|numb[1] fenei:inst8|numb[3] } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns ( 75.00 % ) " "Info: Total cell delay = 6.000 ns ( 75.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 25.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { controller:inst|numb[1] fenei:inst8|numb[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { controller:inst|numb[1] fenei:inst8|numb[3] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-45.000 ns - Smallest " "Info: - Smallest clock skew is -45.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4m destination 75.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk4m\" to destination register is 75.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk4m 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk4m'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clk4m } "NODE_NAME" } "" } } { "traffic_light.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/traffic_light.bdf" { { 0 520 688 16 "clk4m" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns frequency:inst4\|74390:1\|7 2 REG LC122 3 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC122; Fanout = 3; REG Node = 'frequency:inst4\|74390:1\|7'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "1.000 ns" { clk4m frequency:inst4|74390:1|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns frequency:inst4\|74390:1\|3 3 REG LC23 3 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC23; Fanout = 3; REG Node = 'frequency:inst4\|74390:1\|3'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns frequency:inst4\|74390:1\|34 4 REG LC20 3 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC20; Fanout = 3; REG Node = 'frequency:inst4\|74390:1\|34'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 31.000 ns frequency:inst4\|74390:1\|31 5 REG LC30 3 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC30; Fanout = 3; REG Node = 'frequency:inst4\|74390:1\|31'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 40.000 ns frequency:inst4\|74390:2\|7 6 REG LC29 3 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC29; Fanout = 3; REG Node = 'frequency:inst4\|74390:2\|7'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 49.000 ns frequency:inst4\|74390:2\|3 7 REG LC26 3 " "Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 49.000 ns; Loc. = LC26; Fanout = 3; REG Node = 'frequency:inst4\|74390:2\|3'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 58.000 ns frequency:inst4\|74390:2\|34 8 REG LC22 3 " "Info: 8: + IC(2.000 ns) + CELL(7.000 ns) = 58.000 ns; Loc. = LC22; Fanout = 3; REG Node = 'frequency:inst4\|74390:2\|34'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 67.000 ns frequency:inst4\|4 9 REG LC25 53 " "Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 67.000 ns; Loc. = LC25; Fanout = 53; REG Node = 'frequency:inst4\|4'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:2|34 frequency:inst4|4 } "NODE_NAME" } "" } } { "frequency.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/frequency.bdf" { { 24 904 968 104 "4" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 75.000 ns fenei:inst8\|numb\[3\] 10 REG LC44 17 " "Info: 10: + IC(2.000 ns) + CELL(6.000 ns) = 75.000 ns; Loc. = LC44; Fanout = 17; REG Node = 'fenei:inst8\|numb\[3\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { frequency:inst4|4 fenei:inst8|numb[3] } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "59.000 ns ( 78.67 % ) " "Info: Total cell delay = 59.000 ns ( 78.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "16.000 ns ( 21.33 % ) " "Info: Total interconnect delay = 16.000 ns ( 21.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "75.000 ns" { clk4m frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|4 fenei:inst8|numb[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "75.000 ns" { clk4m clk4m~out frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|4 fenei:inst8|numb[3] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk4m source 120.000 ns - Longest register " "Info: - Longest clock path from clock \"clk4m\" to source register is 120.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk4m 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk4m'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clk4m } "NODE_NAME" } "" } } { "traffic_light.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/traffic_light.bdf" { { 0 520 688 16 "clk4m" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns frequency:inst4\|74390:1\|7 2 REG LC122 3 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC122; Fanout = 3; REG Node = 'frequency:inst4\|74390:1\|7'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "1.000 ns" { clk4m frequency:inst4|74390:1|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 13.000 ns frequency:inst4\|74390:1\|3 3 REG LC23 3 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC23; Fanout = 3; REG Node = 'frequency:inst4\|74390:1\|3'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 22.000 ns frequency:inst4\|74390:1\|34 4 REG LC20 3 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC20; Fanout = 3; REG Node = 'frequency:inst4\|74390:1\|34'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 31.000 ns frequency:inst4\|74390:1\|31 5 REG LC30 3 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC30; Fanout = 3; REG Node = 'frequency:inst4\|74390:1\|31'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 40.000 ns frequency:inst4\|74390:2\|7 6 REG LC29 3 " "Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC29; Fanout = 3; REG Node = 'frequency:inst4\|74390:2\|7'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 49.000 ns frequency:inst4\|74390:2\|3 7 REG LC26 3 " "Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 49.000 ns; Loc. = LC26; Fanout = 3; REG Node = 'frequency:inst4\|74390:2\|3'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 58.000 ns frequency:inst4\|74390:2\|34 8 REG LC22 3 " "Info: 8: + IC(2.000 ns) + CELL(7.000 ns) = 58.000 ns; Loc. = LC22; Fanout = 3; REG Node = 'frequency:inst4\|74390:2\|34'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 67.000 ns frequency:inst4\|5 9 REG LC119 3 " "Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 67.000 ns; Loc. = LC119; Fanout = 3; REG Node = 'frequency:inst4\|5'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:2|34 frequency:inst4|5 } "NODE_NAME" } "" } } { "frequency.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/frequency.bdf" { { 24 1008 1072 104 "5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 76.000 ns frequency:inst4\|74390:2\|31 10 REG LC19 3 " "Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 76.000 ns; Loc. = LC19; Fanout = 3; REG Node = 'frequency:inst4\|74390:2\|31'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|5 frequency:inst4|74390:2|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 85.000 ns frequency:inst4\|74390:3\|7 11 REG LC18 3 " "Info: 11: + IC(2.000 ns) + CELL(7.000 ns) = 85.000 ns; Loc. = LC18; Fanout = 3; REG Node = 'frequency:inst4\|74390:3\|7'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:2|31 frequency:inst4|74390:3|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 94.000 ns frequency:inst4\|74390:3\|3 12 REG LC16 3 " "Info: 12: + IC(2.000 ns) + CELL(7.000 ns) = 94.000 ns; Loc. = LC16; Fanout = 3; REG Node = 'frequency:inst4\|74390:3\|3'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:3|7 frequency:inst4|74390:3|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 103.000 ns frequency:inst4\|74390:3\|34 13 REG LC15 3 " "Info: 13: + IC(2.000 ns) + CELL(7.000 ns) = 103.000 ns; Loc. = LC15; Fanout = 3; REG Node = 'frequency:inst4\|74390:3\|34'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:3|3 frequency:inst4|74390:3|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 112.000 ns frequency:inst4\|74390:3\|31 14 REG LC3 26 " "Info: 14: + IC(2.000 ns) + CELL(7.000 ns) = 112.000 ns; Loc. = LC3; Fanout = 26; REG Node = 'frequency:inst4\|74390:3\|31'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "9.000 ns" { frequency:inst4|74390:3|34 frequency:inst4|74390:3|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 120.000 ns controller:inst\|numb\[1\] 15 REG LC36 8 " "Info: 15: + IC(2.000 ns) + CELL(6.000 ns) = 120.000 ns; Loc. = LC36; Fanout = 8; REG Node = 'controller:inst\|numb\[1\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { frequency:inst4|74390:3|31 controller:inst|numb[1] } "NODE_NAME" } "" } } { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "94.000 ns ( 78.33 % ) " "Info: Total cell delay = 94.000 ns ( 78.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "26.000 ns ( 21.67 % ) " "Info: Total interconnect delay = 26.000 ns ( 21.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "120.000 ns" { clk4m frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|5 frequency:inst4|74390:2|31 frequency:inst4|74390:3|7 frequency:inst4|74390:3|3 frequency:inst4|74390:3|34 frequency:inst4|74390:3|31 controller:inst|numb[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "120.000 ns" { clk4m clk4m~out frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|5 frequency:inst4|74390:2|31 frequency:inst4|74390:3|7 frequency:inst4|74390:3|3 frequency:inst4|74390:3|34 frequency:inst4|74390:3|31 controller:inst|numb[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "75.000 ns" { clk4m frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|4 fenei:inst8|numb[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "75.000 ns" { clk4m clk4m~out frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|4 fenei:inst8|numb[3] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "120.000 ns" { clk4m frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|5 frequency:inst4|74390:2|31 frequency:inst4|74390:3|7 frequency:inst4|74390:3|3 frequency:inst4|74390:3|34 frequency:inst4|74390:3|31 controller:inst|numb[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "120.000 ns" { clk4m clk4m~out frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|5 frequency:inst4|74390:2|31 frequency:inst4|74390:3|7 frequency:inst4|74390:3|3 frequency:inst4|74390:3|34 frequency:inst4|74390:3|31 controller:inst|numb[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 40 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" { } { { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { controller:inst|numb[1] fenei:inst8|numb[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "8.000 ns" { controller:inst|numb[1] fenei:inst8|numb[3] } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "75.000 ns" { clk4m frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|4 fenei:inst8|numb[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "75.000 ns" { clk4m clk4m~out frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|4 fenei:inst8|numb[3] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "traffic_light" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/traffic_light.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "120.000 ns" { clk4m frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|5 frequency:inst4|74390:2|31 frequency:inst4|74390:3|7 frequency:inst4|74390:3|3 frequency:inst4|74390:3|34 frequency:inst4|74390:3|31 controller:inst|numb[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "120.000 ns" { clk4m clk4m~out frequency:inst4|74390:1|7 frequency:inst4|74390:1|3 frequency:inst4|74390:1|34 frequency:inst4|74390:1|31 frequency:inst4|74390:2|7 frequency:inst4|74390:2|3 frequency:inst4|74390:2|34 frequency:inst4|5 frequency:inst4|74390:2|31 frequency:inst4|74390:3|7 frequency:inst4|74390:3|3 frequency:inst4|74390:3|34 frequency:inst4|74390:3|31 controller:inst|numb[1] } { 0.000ns 0.000ns 0.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 7.000ns 6.000ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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