traffic_light.map.qmsg

CPLD控制交通灯程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version " "Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 06 10:46:45 2007 " "Info: Processing started: Mon Aug 06 10:46:45 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic_light -c traffic_light " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic_light -c traffic_light" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic_light.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file traffic_light.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 traffic_light " "Info: Found entity 1: traffic_light" {  } { { "traffic_light.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/traffic_light.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "traffic_light " "Info: Elaborating entity \"traffic_light\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "controller.vhd 2 1 " "Warning: Using design file controller.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 controller-a " "Info: Found design unit 1: controller-a" {  } { { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 controller " "Info: Found entity 1: controller" {  } { { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "controller controller:inst " "Info: Elaborating entity \"controller\" for hierarchy \"controller:inst\"" {  } { { "traffic_light.bdf" "inst" { Schematic "E:/CPLD/Program/VHDL/traffic_light/traffic_light.bdf" { { -32 944 1080 160 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "reset controller.vhd(22) " "Warning (10492): VHDL Process Statement warning at controller.vhd(22): signal \"reset\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "controller.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/controller.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "frequency.bdf 1 1 " "Warning: Using design file frequency.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 frequency " "Info: Found entity 1: frequency" {  } { { "frequency.bdf" "" { Schematic "E:/CPLD/Program/VHDL/traffic_light/frequency.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "frequency frequency:inst4 " "Info: Elaborating entity \"frequency\" for hierarchy \"frequency:inst4\"" {  } { { "traffic_light.bdf" "inst4" { Schematic "E:/CPLD/Program/VHDL/traffic_light/traffic_light.bdf" { { -24 688 800 72 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74390 " "Info: Found entity 1: 74390" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus51/libraries/others/maxplus2/74390.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74390 frequency:inst4\|74390:2 " "Info: Elaborating entity \"74390\" for hierarchy \"frequency:inst4\|74390:2\"" {  } { { "frequency.bdf" "2" { Schematic "E:/CPLD/Program/VHDL/traffic_light/frequency.bdf" { { 136 656 768 296 "2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "leddongtai.vhd 2 1 " "Warning: Using design file leddongtai.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 leddongtai-one " "Info: Found design unit 1: leddongtai-one" {  } { { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 leddongtai " "Info: Found entity 1: leddongtai" {  } { { "leddongtai.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/leddongtai.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "leddongtai leddongtai:inst3 " "Info: Elaborating entity \"leddongtai\" for hierarchy \"leddongtai:inst3\"" {  } { { "traffic_light.bdf" "inst3" { Schematic "E:/CPLD/Program/VHDL/traffic_light/traffic_light.bdf" { { 288 1216 1376 448 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "display.vhd 2 1 " "Warning: Using design file display.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-light " "Info: Found design unit 1: display-light" {  } { { "display.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/display.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "display.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/display.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display display:inst1 " "Info: Elaborating entity \"display\" for hierarchy \"display:inst1\"" {  } { { "traffic_light.bdf" "inst1" { Schematic "E:/CPLD/Program/VHDL/traffic_light/traffic_light.bdf" { { 184 936 1088 280 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "fenei.vhd 2 1 " "Warning: Using design file fenei.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenei-a " "Info: Found design unit 1: fenei-a" {  } { { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 fenei " "Info: Found entity 1: fenei" {  } { { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenei fenei:inst2 " "Info: Elaborating entity \"fenei\" for hierarchy \"fenei:inst2\"" {  } { { "traffic_light.bdf" "inst2" { Schematic "E:/CPLD/Program/VHDL/traffic_light/traffic_light.bdf" { { 248 552 712 344 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}