fenei.tan.qmsg

CPLD控制交通灯程序

{ "Info" "ITAN_NO_REG2REG_EXIST" "clock " "Info: No valid register-to-register data paths exist for clock \"clock\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "numb\[2\]~reg0 numin\[1\] clock 11.000 ns register " "Info: tsu for register \"numb\[2\]~reg0\" (data pin = \"numin\[1\]\", clock pin = \"clock\") is 11.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns + Longest pin register " "Info: + Longest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns numin\[1\] 1 PIN PIN_81 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 7; PIN Node = 'numin\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { numin[1] } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns numb\[2\]~reg0 2 REG LC8 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'numb\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { numin[1] numb[2]~reg0 } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "10.000 ns" { numin[1] numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { numin[1] numin[1]~out numb[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns numb\[2\]~reg0 2 REG LC8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'numb\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock numb[2]~reg0 } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numb[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "10.000 ns" { numin[1] numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { numin[1] numin[1]~out numb[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numb[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock numb\[3\] numb\[3\]~reg0 8.000 ns register " "Info: tco from clock \"clock\" to destination pin \"numb\[3\]\" through register \"numb\[3\]~reg0\" is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns numb\[3\]~reg0 2 REG LC14 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC14; Fanout = 1; REG Node = 'numb\[3\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock numb[3]~reg0 } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numb[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numb[3]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register pin " "Info: + Longest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns numb\[3\]~reg0 1 REG LC14 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC14; Fanout = 1; REG Node = 'numb\[3\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { numb[3]~reg0 } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns numb\[3\] 2 PIN PIN_5 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'numb\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "4.000 ns" { numb[3]~reg0 numb[3] } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 100.00 % ) " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "4.000 ns" { numb[3]~reg0 numb[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { numb[3]~reg0 numb[3] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numb[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numb[3]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "4.000 ns" { numb[3]~reg0 numb[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.000 ns" { numb[3]~reg0 numb[3] } { 0.000ns 0.000ns } { 0.000ns 4.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "numb\[2\]~reg0 numin\[1\] clock -3.000 ns register " "Info: th for register \"numb\[2\]~reg0\" (data pin = \"numin\[1\]\", clock pin = \"clock\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clock 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clock'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { clock } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns numb\[2\]~reg0 2 REG LC8 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'numb\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "0.000 ns" { clock numb[2]~reg0 } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 100.00 % ) " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numb[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns numin\[1\] 1 PIN PIN_81 7 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 7; PIN Node = 'numin\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "" { numin[1] } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns numb\[2\]~reg0 2 REG LC8 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'numb\[2\]~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "8.000 ns" { numin[1] numb[2]~reg0 } "NODE_NAME" } "" } } { "fenei.vhd" "" { Text "E:/CPLD/Program/VHDL/traffic_light/fenei.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "10.000 ns" { numin[1] numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { numin[1] numin[1]~out numb[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "3.000 ns" { clock numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.000 ns" { clock clock~out numb[2]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "fenei" "UNKNOWN" "V1" "E:/CPLD/Program/VHDL/traffic_light/db/fenei.quartus_db" { Floorplan "E:/CPLD/Program/VHDL/traffic_light/" "" "10.000 ns" { numin[1] numb[2]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.000 ns" { numin[1] numin[1]~out numb[2]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 05 22:48:34 2007 " "Info: Processing ended: Sun Aug 05 22:48:34 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}