traffic_light.hier_info

CPLD控制交通灯程序

|traffic_light
reda <= controller:inst.reda
clk4m => frequency:inst4.clk4m
reset => controller:inst.reset
hold => controller:inst.hold
greena <= controller:inst.greena
yellowa <= controller:inst.yellowa
redb <= controller:inst.redb
greenb <= controller:inst.greenb
yellowb <= controller:inst.yellowb
clkl <= frequency:inst4.clk1
clk1k <= frequency:inst4.clk1k
dp <= leddongtai:inst3.dp
leddisp[0] <= leddongtai:inst3.leddisp[0]
leddisp[1] <= leddongtai:inst3.leddisp[1]
leddisp[2] <= leddongtai:inst3.leddisp[2]
leddisp[3] <= leddongtai:inst3.leddisp[3]
leddisp[4] <= leddongtai:inst3.leddisp[4]
leddisp[5] <= leddongtai:inst3.leddisp[5]
leddisp[6] <= leddongtai:inst3.leddisp[6]
sel[0] <= leddongtai:inst3.sel[0]
sel[1] <= leddongtai:inst3.sel[1]
sel[2] <= leddongtai:inst3.sel[2]
sel[3] <= leddongtai:inst3.sel[3]


|traffic_light|controller:inst
clock => countnum[4].CLK
clock => countnum[3].CLK
clock => countnum[2].CLK
clock => countnum[1].CLK
clock => countnum[0].CLK
clock => flash~reg0.CLK
clock => reda~reg0.CLK
clock => redb~reg0.CLK
clock => greena~reg0.CLK
clock => greenb~reg0.CLK
clock => yellowa~reg0.CLK
clock => yellowb~reg0.CLK
clock => numa[4]~reg0.CLK
clock => numa[3]~reg0.CLK
clock => numa[2]~reg0.CLK
clock => numa[1]~reg0.CLK
clock => numa[0]~reg0.CLK
clock => numb[4]~reg0.CLK
clock => numb[3]~reg0.CLK
clock => numb[2]~reg0.CLK
clock => numb[1]~reg0.CLK
clock => numb[0]~reg0.CLK
clock => countnum[5].CLK
reset => process0~0.IN0
hold => process0~1.IN0
flash <= flash~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[0] <= numa[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[1] <= numa[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[2] <= numa[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[3] <= numa[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[4] <= numa[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[0] <= numb[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[1] <= numb[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[2] <= numb[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[3] <= numb[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[4] <= numb[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
reda <= reda~reg0.DB_MAX_OUTPUT_PORT_TYPE
greena <= greena~reg0.DB_MAX_OUTPUT_PORT_TYPE
yellowa <= yellowa~reg0.DB_MAX_OUTPUT_PORT_TYPE
redb <= redb~reg0.DB_MAX_OUTPUT_PORT_TYPE
greenb <= greenb~reg0.DB_MAX_OUTPUT_PORT_TYPE
yellowb <= yellowb~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_light|frequency:inst4
clk1k <= 4.DB_MAX_OUTPUT_PORT_TYPE
clk4m => 74390:1.1CLKA
clk1 <= 74390:3.2QD


|traffic_light|frequency:inst4|74390:2
2QA <= 34.DB_MAX_OUTPUT_PORT_TYPE
2CLR => 25.IN0
2CLKA => 24.IN0
2QB <= 33.DB_MAX_OUTPUT_PORT_TYPE
2QD <= 31.DB_MAX_OUTPUT_PORT_TYPE
2QC <= 32.DB_MAX_OUTPUT_PORT_TYPE
2CLKB => 27.IN0
2CLKB => 29.IN1
1QD <= 3.DB_MAX_OUTPUT_PORT_TYPE
1CLR => 22.IN0
1QC <= 5.DB_MAX_OUTPUT_PORT_TYPE
1QB <= 6.DB_MAX_OUTPUT_PORT_TYPE
1CLKB => 20.IN1
1CLKB => 17.IN0
1QA <= 7.DB_MAX_OUTPUT_PORT_TYPE
1CLKA => 23.IN0


|traffic_light|frequency:inst4|74390:1
2QA <= 34.DB_MAX_OUTPUT_PORT_TYPE
2CLR => 25.IN0
2CLKA => 24.IN0
2QB <= 33.DB_MAX_OUTPUT_PORT_TYPE
2QD <= 31.DB_MAX_OUTPUT_PORT_TYPE
2QC <= 32.DB_MAX_OUTPUT_PORT_TYPE
2CLKB => 27.IN0
2CLKB => 29.IN1
1QD <= 3.DB_MAX_OUTPUT_PORT_TYPE
1CLR => 22.IN0
1QC <= 5.DB_MAX_OUTPUT_PORT_TYPE
1QB <= 6.DB_MAX_OUTPUT_PORT_TYPE
1CLKB => 20.IN1
1CLKB => 17.IN0
1QA <= 7.DB_MAX_OUTPUT_PORT_TYPE
1CLKA => 23.IN0


|traffic_light|frequency:inst4|74390:3
2QA <= 34.DB_MAX_OUTPUT_PORT_TYPE
2CLR => 25.IN0
2CLKA => 24.IN0
2QB <= 33.DB_MAX_OUTPUT_PORT_TYPE
2QD <= 31.DB_MAX_OUTPUT_PORT_TYPE
2QC <= 32.DB_MAX_OUTPUT_PORT_TYPE
2CLKB => 27.IN0
2CLKB => 29.IN1
1QD <= 3.DB_MAX_OUTPUT_PORT_TYPE
1CLR => 22.IN0
1QC <= 5.DB_MAX_OUTPUT_PORT_TYPE
1QB <= 6.DB_MAX_OUTPUT_PORT_TYPE
1CLKB => 20.IN1
1CLKB => 17.IN0
1QA <= 7.DB_MAX_OUTPUT_PORT_TYPE
1CLKA => 23.IN0


|traffic_light|leddongtai:inst3
clock => count[1].CLK
clock => count[0].CLK
clock => leddisp[6]~reg0.CLK
clock => leddisp[5]~reg0.CLK
clock => leddisp[4]~reg0.CLK
clock => leddisp[3]~reg0.CLK
clock => leddisp[2]~reg0.CLK
clock => leddisp[1]~reg0.CLK
clock => leddisp[0]~reg0.CLK
clock => sel[3]~reg0.CLK
clock => sel[2]~reg0.CLK
clock => sel[1]~reg0.CLK
clock => sel[0]~reg0.CLK
clock => count[2].CLK
flash => count~3.OUTPUTSELECT
flash => count~4.OUTPUTSELECT
flash => count~5.OUTPUTSELECT
ewh[0] => Mux~6.IN4
ewh[1] => Mux~5.IN4
ewh[2] => Mux~4.IN4
ewh[3] => Mux~3.IN4
ewh[4] => Mux~2.IN4
ewh[5] => Mux~1.IN4
ewh[6] => Mux~0.IN4
ewl[0] => Mux~6.IN5
ewl[1] => Mux~5.IN5
ewl[2] => Mux~4.IN5
ewl[3] => Mux~3.IN5
ewl[4] => Mux~2.IN5
ewl[5] => Mux~1.IN5
ewl[6] => Mux~0.IN5
snh[0] => Mux~6.IN6
snh[1] => Mux~5.IN6
snh[2] => Mux~4.IN6
snh[3] => Mux~3.IN6
snh[4] => Mux~2.IN6
snh[5] => Mux~1.IN6
snh[6] => Mux~0.IN6
snl[0] => Mux~6.IN7
snl[1] => Mux~5.IN7
snl[2] => Mux~4.IN7
snl[3] => Mux~3.IN7
snl[4] => Mux~2.IN7
snl[5] => Mux~1.IN7
snl[6] => Mux~0.IN7
leddisp[0] <= leddisp[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
leddisp[1] <= leddisp[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
leddisp[2] <= leddisp[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
leddisp[3] <= leddisp[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
leddisp[4] <= leddisp[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
leddisp[5] <= leddisp[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
leddisp[6] <= leddisp[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[0] <= sel[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[1] <= sel[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[2] <= sel[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[3] <= sel[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp <= <VCC>


|traffic_light|display:inst1
clock => display[5]~reg0.CLK
clock => display[4]~reg0.CLK
clock => display[3]~reg0.CLK
clock => display[2]~reg0.CLK
clock => display[1]~reg0.CLK
clock => display[0]~reg0.CLK
clock => display[6]~reg0.CLK
qin[0] => Mux~0.IN19
qin[0] => Mux~1.IN19
qin[0] => Mux~2.IN19
qin[0] => Mux~3.IN19
qin[0] => Mux~4.IN19
qin[0] => Mux~5.IN19
qin[0] => Mux~6.IN19
qin[1] => Mux~0.IN18
qin[1] => Mux~1.IN18
qin[1] => Mux~2.IN18
qin[1] => Mux~3.IN18
qin[1] => Mux~4.IN18
qin[1] => Mux~5.IN18
qin[1] => Mux~6.IN18
qin[2] => Mux~0.IN17
qin[2] => Mux~1.IN17
qin[2] => Mux~2.IN17
qin[2] => Mux~3.IN17
qin[2] => Mux~4.IN17
qin[2] => Mux~5.IN17
qin[2] => Mux~6.IN17
qin[3] => Mux~0.IN16
qin[3] => Mux~1.IN16
qin[3] => Mux~2.IN16
qin[3] => Mux~3.IN16
qin[3] => Mux~4.IN16
qin[3] => Mux~5.IN16
qin[3] => Mux~6.IN16
display[0] <= display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[1] <= display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[2] <= display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[3] <= display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[4] <= display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[5] <= display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[6] <= display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_light|fenei:inst2
clock => numa[2]~reg0.CLK
clock => numa[1]~reg0.CLK
clock => numa[0]~reg0.CLK
clock => numb[3]~reg0.CLK
clock => numb[2]~reg0.CLK
clock => numb[1]~reg0.CLK
clock => numb[0]~reg0.CLK
clock => numa[3]~reg0.CLK
numin[0] => LessThan~0.IN10
numin[0] => LessThan~1.IN10
numin[0] => numb[0]~reg0.DATAIN
numin[1] => LessThan~0.IN9
numin[1] => LessThan~1.IN9
numin[1] => add~1.IN8
numin[1] => numb~2.DATAA
numin[1] => numb~5.DATAB
numin[2] => LessThan~0.IN8
numin[2] => add~0.IN6
numin[2] => LessThan~1.IN8
numin[2] => add~1.IN7
numin[2] => numb~1.DATAA
numin[3] => LessThan~0.IN7
numin[3] => add~0.IN5
numin[3] => LessThan~1.IN7
numin[3] => add~1.IN6
numin[3] => numb~0.DATAA
numin[4] => LessThan~0.IN6
numin[4] => add~0.IN4
numin[4] => LessThan~1.IN6
numin[4] => add~1.IN5
numa[0] <= numa[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[1] <= numa[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[2] <= numa[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[3] <= numa[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[0] <= numb[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[1] <= numb[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[2] <= numb[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[3] <= numb[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_light|display:inst5
clock => display[5]~reg0.CLK
clock => display[4]~reg0.CLK
clock => display[3]~reg0.CLK
clock => display[2]~reg0.CLK
clock => display[1]~reg0.CLK
clock => display[0]~reg0.CLK
clock => display[6]~reg0.CLK
qin[0] => Mux~0.IN19
qin[0] => Mux~1.IN19
qin[0] => Mux~2.IN19
qin[0] => Mux~3.IN19
qin[0] => Mux~4.IN19
qin[0] => Mux~5.IN19
qin[0] => Mux~6.IN19
qin[1] => Mux~0.IN18
qin[1] => Mux~1.IN18
qin[1] => Mux~2.IN18
qin[1] => Mux~3.IN18
qin[1] => Mux~4.IN18
qin[1] => Mux~5.IN18
qin[1] => Mux~6.IN18
qin[2] => Mux~0.IN17
qin[2] => Mux~1.IN17
qin[2] => Mux~2.IN17
qin[2] => Mux~3.IN17
qin[2] => Mux~4.IN17
qin[2] => Mux~5.IN17
qin[2] => Mux~6.IN17
qin[3] => Mux~0.IN16
qin[3] => Mux~1.IN16
qin[3] => Mux~2.IN16
qin[3] => Mux~3.IN16
qin[3] => Mux~4.IN16
qin[3] => Mux~5.IN16
qin[3] => Mux~6.IN16
display[0] <= display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[1] <= display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[2] <= display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[3] <= display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[4] <= display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[5] <= display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[6] <= display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_light|display:inst6
clock => display[5]~reg0.CLK
clock => display[4]~reg0.CLK
clock => display[3]~reg0.CLK
clock => display[2]~reg0.CLK
clock => display[1]~reg0.CLK
clock => display[0]~reg0.CLK
clock => display[6]~reg0.CLK
qin[0] => Mux~0.IN19
qin[0] => Mux~1.IN19
qin[0] => Mux~2.IN19
qin[0] => Mux~3.IN19
qin[0] => Mux~4.IN19
qin[0] => Mux~5.IN19
qin[0] => Mux~6.IN19
qin[1] => Mux~0.IN18
qin[1] => Mux~1.IN18
qin[1] => Mux~2.IN18
qin[1] => Mux~3.IN18
qin[1] => Mux~4.IN18
qin[1] => Mux~5.IN18
qin[1] => Mux~6.IN18
qin[2] => Mux~0.IN17
qin[2] => Mux~1.IN17
qin[2] => Mux~2.IN17
qin[2] => Mux~3.IN17
qin[2] => Mux~4.IN17
qin[2] => Mux~5.IN17
qin[2] => Mux~6.IN17
qin[3] => Mux~0.IN16
qin[3] => Mux~1.IN16
qin[3] => Mux~2.IN16
qin[3] => Mux~3.IN16
qin[3] => Mux~4.IN16
qin[3] => Mux~5.IN16
qin[3] => Mux~6.IN16
display[0] <= display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[1] <= display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[2] <= display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[3] <= display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[4] <= display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[5] <= display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[6] <= display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_light|fenei:inst8
clock => numa[2]~reg0.CLK
clock => numa[1]~reg0.CLK
clock => numa[0]~reg0.CLK
clock => numb[3]~reg0.CLK
clock => numb[2]~reg0.CLK
clock => numb[1]~reg0.CLK
clock => numb[0]~reg0.CLK
clock => numa[3]~reg0.CLK
numin[0] => LessThan~0.IN10
numin[0] => LessThan~1.IN10
numin[0] => numb[0]~reg0.DATAIN
numin[1] => LessThan~0.IN9
numin[1] => LessThan~1.IN9
numin[1] => add~1.IN8
numin[1] => numb~2.DATAA
numin[1] => numb~5.DATAB
numin[2] => LessThan~0.IN8
numin[2] => add~0.IN6
numin[2] => LessThan~1.IN8
numin[2] => add~1.IN7
numin[2] => numb~1.DATAA
numin[3] => LessThan~0.IN7
numin[3] => add~0.IN5
numin[3] => LessThan~1.IN7
numin[3] => add~1.IN6
numin[3] => numb~0.DATAA
numin[4] => LessThan~0.IN6
numin[4] => add~0.IN4
numin[4] => LessThan~1.IN6
numin[4] => add~1.IN5
numa[0] <= numa[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[1] <= numa[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[2] <= numa[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numa[3] <= numa[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[0] <= numb[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[1] <= numb[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[2] <= numb[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
numb[3] <= numb[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|traffic_light|display:inst7
clock => display[5]~reg0.CLK
clock => display[4]~reg0.CLK
clock => display[3]~reg0.CLK
clock => display[2]~reg0.CLK
clock => display[1]~reg0.CLK
clock => display[0]~reg0.CLK
clock => display[6]~reg0.CLK
qin[0] => Mux~0.IN19
qin[0] => Mux~1.IN19
qin[0] => Mux~2.IN19
qin[0] => Mux~3.IN19
qin[0] => Mux~4.IN19
qin[0] => Mux~5.IN19
qin[0] => Mux~6.IN19
qin[1] => Mux~0.IN18
qin[1] => Mux~1.IN18
qin[1] => Mux~2.IN18
qin[1] => Mux~3.IN18
qin[1] => Mux~4.IN18
qin[1] => Mux~5.IN18
qin[1] => Mux~6.IN18
qin[2] => Mux~0.IN17
qin[2] => Mux~1.IN17
qin[2] => Mux~2.IN17
qin[2] => Mux~3.IN17
qin[2] => Mux~4.IN17
qin[2] => Mux~5.IN17
qin[2] => Mux~6.IN17
qin[3] => Mux~0.IN16
qin[3] => Mux~1.IN16
qin[3] => Mux~2.IN16
qin[3] => Mux~3.IN16
qin[3] => Mux~4.IN16
qin[3] => Mux~5.IN16
qin[3] => Mux~6.IN16
display[0] <= display[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[1] <= display[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[2] <= display[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[3] <= display[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[4] <= display[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[5] <= display[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
display[6] <= display[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE