controller.tan.rpt

CPLD控制交通灯程序

+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 8.000 ns   ; numa[4]~reg0 ; numa[4] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numb[4]~reg0 ; numb[4] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numb[3]~reg0 ; numb[3] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numb[2]~reg0 ; numb[2] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numa[3]~reg0 ; numa[3] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numa[2]~reg0 ; numa[2] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numa[1]~reg0 ; numa[1] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numa[0]~reg0 ; numa[0] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; yellowb~reg0 ; yellowb ; clock      ;
; N/A   ; None         ; 8.000 ns   ; greenb~reg0  ; greenb  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numb[1]~reg0 ; numb[1] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; redb~reg0    ; redb    ; clock      ;
; N/A   ; None         ; 8.000 ns   ; yellowa~reg0 ; yellowa ; clock      ;
; N/A   ; None         ; 8.000 ns   ; greena~reg0  ; greena  ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numb[0]~reg0 ; numb[0] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; reda~reg0    ; reda    ; clock      ;
; N/A   ; None         ; 8.000 ns   ; flash~reg0   ; flash   ; clock      ;
+-------+--------------+------------+--------------+---------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+-------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To           ; To Clock ;
+---------------+-------------+-----------+-------+--------------+----------+
; N/A           ; None        ; -3.000 ns ; reset ; flash~reg0   ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; countnum[0]  ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; flash~reg0   ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; countnum[1]  ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; countnum[5]  ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; countnum[4]  ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; countnum[3]  ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; countnum[2]  ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; reda~reg0    ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; redb~reg0    ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; greena~reg0  ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; yellowa~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; numb[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; greenb~reg0  ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; yellowb~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; numb[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; numa[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; numa[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; numa[3]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; numa[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; numb[4]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; numb[3]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; numb[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; hold  ; numa[4]~reg0 ; clock    ;
+---------------+-------------+-----------+-------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Aug 06 10:30:44 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off controller -c controller
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 66.67 MHz between source register "countnum[1]" and destination register "numb[2]~reg0" (period= 15.0 ns)
    Info: + Longest register to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC9; Fanout = 60; REG Node = 'countnum[1]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC22; Fanout = 1; COMB Node = 'numb~1983'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC23; Fanout = 1; COMB Node = 'numb~1985'
        Info: 4: + IC(0.000 ns) + CELL(1.000 ns) = 10.000 ns; Loc. = LC24; Fanout = 1; REG Node = 'numb[2]~reg0'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 23; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC24; Fanout = 1; REG Node = 'numb[2]~reg0'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock "clock" to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 23; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC9; Fanout = 60; REG Node = 'countnum[1]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "greenb~reg0" (data pin = "hold", clock pin = "clock") is 12.000 ns
    Info: + Longest pin to register delay is 11.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 31; PIN Node = 'hold'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC18; Fanout = 1; COMB Node = 'greenb~47'
        Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC19; Fanout = 1; REG Node = 'greenb~reg0'
        Info: Total cell delay = 9.000 ns ( 81.82 % )
        Info: Total interconnect delay = 2.000 ns ( 18.18 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "clock" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 23; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC19; Fanout = 1; REG Node = 'greenb~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "clock" to destination pin "numa[4]" through register "numa[4]~reg0" is 8.000 ns
    Info: + Longest clock path from clock "clock" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 23; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC21; Fanout = 1; REG Node = 'numa[4]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 1; REG Node = 'numa[4]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'numa[4]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: th for register "flash~reg0" (data pin = "reset", clock pin = "clock") is -3.000 ns
    Info: + Longest clock path from clock "clock" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 23; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'flash~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 7; PIN Node = 'reset'
        Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'flash~reg0'
        Info: Total cell delay = 9.000 ns ( 90.00 % )
        Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Mon Aug 06 10:30:44 2007
    Info: Elapsed time: 00:00:01