📄 traffic_light.map.rpt
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; |traffic_light ; 117 ; 23 ; |traffic_light ;
; |controller:inst| ; 34 ; 0 ; |traffic_light|controller:inst ;
; |display:inst1| ; 5 ; 0 ; |traffic_light|display:inst1 ;
; |display:inst5| ; 7 ; 0 ; |traffic_light|display:inst5 ;
; |display:inst6| ; 5 ; 0 ; |traffic_light|display:inst6 ;
; |display:inst7| ; 7 ; 0 ; |traffic_light|display:inst7 ;
; |fenei:inst2| ; 6 ; 0 ; |traffic_light|fenei:inst2 ;
; |fenei:inst8| ; 6 ; 0 ; |traffic_light|fenei:inst8 ;
; |frequency:inst4| ; 26 ; 0 ; |traffic_light|frequency:inst4 ;
; |74390:1| ; 8 ; 0 ; |traffic_light|frequency:inst4|74390:1 ;
; |74390:2| ; 8 ; 0 ; |traffic_light|frequency:inst4|74390:2 ;
; |74390:3| ; 8 ; 0 ; |traffic_light|frequency:inst4|74390:3 ;
; |leddongtai:inst3| ; 20 ; 0 ; |traffic_light|leddongtai:inst3 ;
+----------------------------+------------+------+----------------------------------------+
+----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: controller:inst|lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+-------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-------------------------------------------------+
; LPM_WIDTH ; 6 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_pnh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: controller:inst|lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+-------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-------------------------------------------------+
; LPM_WIDTH ; 5 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_uch ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/CPLD/Program/VHDL/traffic_light/traffic_light.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Mon Aug 06 10:46:45 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic_light -c traffic_light
Info: Found 1 design units, including 1 entities, in source file traffic_light.bdf
Info: Found entity 1: traffic_light
Info: Elaborating entity "traffic_light" for the top level hierarchy
Warning: Using design file controller.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: controller-a
Info: Found entity 1: controller
Info: Elaborating entity "controller" for hierarchy "controller:inst"
Warning (10492): VHDL Process Statement warning at controller.vhd(22): signal "reset" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file frequency.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: frequency
Info: Elaborating entity "frequency" for hierarchy "frequency:inst4"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/others/maxplus2/74390.bdf
Info: Found entity 1: 74390
Info: Elaborating entity "74390" for hierarchy "frequency:inst4|74390:2"
Warning: Using design file leddongtai.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: leddongtai-one
Info: Found entity 1: leddongtai
Info: Elaborating entity "leddongtai" for hierarchy "leddongtai:inst3"
Warning: Using design file display.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: display-light
Info: Found entity 1: display
Info: Elaborating entity "display" for hierarchy "display:inst1"
Warning: Using design file fenei.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: fenei-a
Info: Found entity 1: fenei
Info: Elaborating entity "fenei" for hierarchy "fenei:inst2"
Warning: Reduced register "fenei:inst8|numa[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "fenei:inst8|numa[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "fenei:inst2|numa[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "fenei:inst2|numa[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "display:inst1|display[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "display:inst6|display[1]" with stuck data_in port to stuck value GND
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Ignored 13 buffer(s)
Info: Ignored 13 SOFT buffer(s)
Info: Duplicate registers merged to single register
Info: Duplicate register "display:inst1|display[0]" merged to single register "display:inst1|display[3]"
Info: Duplicate register "display:inst6|display[0]" merged to single register "display:inst6|display[3]"
Warning: Output pins are stuck at VCC or GND
Warning: Pin "dp" stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "clk4m" to global clock signal
Info: Implemented 148 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 20 output pins
Info: Implemented 117 macrocells
Info: Implemented 8 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
Info: Processing ended: Mon Aug 06 10:46:54 2007
Info: Elapsed time: 00:00:10
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