📄 leddongtai.tan.rpt
字号:
; N/A ; None ; 11.000 ns ; ewh[0] ; leddisp[0]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; ewl[0] ; leddisp[0]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; snh[0] ; leddisp[0]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; snl[0] ; leddisp[0]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; ewh[1] ; leddisp[1]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; ewl[1] ; leddisp[1]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; snh[1] ; leddisp[1]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; snl[1] ; leddisp[1]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; ewh[3] ; leddisp[3]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; ewl[3] ; leddisp[3]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; snh[3] ; leddisp[3]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; snl[3] ; leddisp[3]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; ewh[5] ; leddisp[5]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; ewl[5] ; leddisp[5]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; snh[5] ; leddisp[5]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; snl[5] ; leddisp[5]~reg0 ; clock ;
; N/A ; None ; 11.000 ns ; flash ; count[0] ; clock ;
; N/A ; None ; 11.000 ns ; flash ; count[2] ; clock ;
; N/A ; None ; 11.000 ns ; flash ; count[1] ; clock ;
+-------+--------------+------------+--------+-----------------+----------+
+-------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-----------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-----------------+------------+------------+
; N/A ; None ; 8.000 ns ; leddisp[6]~reg0 ; leddisp[6] ; clock ;
; N/A ; None ; 8.000 ns ; leddisp[4]~reg0 ; leddisp[4] ; clock ;
; N/A ; None ; 8.000 ns ; leddisp[2]~reg0 ; leddisp[2] ; clock ;
; N/A ; None ; 8.000 ns ; sel[1]~reg0 ; sel[1] ; clock ;
; N/A ; None ; 8.000 ns ; sel[0]~reg0 ; sel[0] ; clock ;
; N/A ; None ; 8.000 ns ; leddisp[5]~reg0 ; leddisp[5] ; clock ;
; N/A ; None ; 8.000 ns ; leddisp[3]~reg0 ; leddisp[3] ; clock ;
; N/A ; None ; 8.000 ns ; leddisp[1]~reg0 ; leddisp[1] ; clock ;
; N/A ; None ; 8.000 ns ; leddisp[0]~reg0 ; leddisp[0] ; clock ;
; N/A ; None ; 8.000 ns ; sel[2]~reg0 ; sel[2] ; clock ;
; N/A ; None ; 8.000 ns ; sel[3]~reg0 ; sel[3] ; clock ;
+-------+--------------+------------+-----------------+------------+------------+
+-------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+--------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+--------+-----------------+----------+
; N/A ; None ; -3.000 ns ; snl[2] ; leddisp[2]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewl[2] ; leddisp[2]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snh[2] ; leddisp[2]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewh[2] ; leddisp[2]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snl[4] ; leddisp[4]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewl[4] ; leddisp[4]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snh[4] ; leddisp[4]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewh[4] ; leddisp[4]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snl[6] ; leddisp[6]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewl[6] ; leddisp[6]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snh[6] ; leddisp[6]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewh[6] ; leddisp[6]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewh[0] ; leddisp[0]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewl[0] ; leddisp[0]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snh[0] ; leddisp[0]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snl[0] ; leddisp[0]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewh[1] ; leddisp[1]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewl[1] ; leddisp[1]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snh[1] ; leddisp[1]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snl[1] ; leddisp[1]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewh[3] ; leddisp[3]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewl[3] ; leddisp[3]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snh[3] ; leddisp[3]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snl[3] ; leddisp[3]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewh[5] ; leddisp[5]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; ewl[5] ; leddisp[5]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snh[5] ; leddisp[5]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; snl[5] ; leddisp[5]~reg0 ; clock ;
; N/A ; None ; -3.000 ns ; flash ; count[0] ; clock ;
; N/A ; None ; -3.000 ns ; flash ; count[2] ; clock ;
; N/A ; None ; -3.000 ns ; flash ; count[1] ; clock ;
+---------------+-------------+-----------+--------+-----------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
Info: Processing started: Mon Aug 06 10:40:51 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off leddongtai -c leddongtai
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 76.92 MHz between source register "count[0]" and destination register "leddisp[2]~reg0" (period= 13.0 ns)
Info: + Longest register to register delay is 8.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 35; REG Node = 'count[0]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'leddisp[2]~reg0'
Info: Total cell delay = 6.000 ns ( 75.00 % )
Info: Total interconnect delay = 2.000 ns ( 25.00 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clock" to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'leddisp[2]~reg0'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: - Longest clock path from clock "clock" to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC1; Fanout = 35; REG Node = 'count[0]'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register "leddisp[2]~reg0" (data pin = "snl[2]", clock pin = "clock") is 11.000 ns
Info: + Longest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_50; Fanout = 1; PIN Node = 'snl[2]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'leddisp[2]~reg0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: + Micro setup delay of destination is 4.000 ns
Info: - Shortest clock path from clock "clock" to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'leddisp[2]~reg0'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "clock" to destination pin "leddisp[6]" through register "leddisp[6]~reg0" is 8.000 ns
Info: + Longest clock path from clock "clock" to source register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC21; Fanout = 1; REG Node = 'leddisp[6]~reg0'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro clock to output delay of source is 1.000 ns
Info: + Longest register to pin delay is 4.000 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 1; REG Node = 'leddisp[6]~reg0'
Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_20; Fanout = 0; PIN Node = 'leddisp[6]'
Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: th for register "leddisp[2]~reg0" (data pin = "snl[2]", clock pin = "clock") is -3.000 ns
Info: + Longest clock path from clock "clock" to destination register is 3.000 ns
Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 14; CLK Node = 'clock'
Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'leddisp[2]~reg0'
Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: + Micro hold delay of destination is 4.000 ns
Info: - Shortest pin to register delay is 10.000 ns
Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_50; Fanout = 1; PIN Node = 'snl[2]'
Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'leddisp[2]~reg0'
Info: Total cell delay = 8.000 ns ( 80.00 % )
Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
Info: Processing ended: Mon Aug 06 10:40:51 2007
Info: Elapsed time: 00:00:01
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -