frequency.tan.rpt

CPLD控制交通灯程序

            Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 67.000 ns; Loc. = LC15; Fanout = 3; REG Node = '5'
            Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 76.000 ns; Loc. = LC19; Fanout = 3; REG Node = '74390:2|31'
            Info: 11: + IC(2.000 ns) + CELL(7.000 ns) = 85.000 ns; Loc. = LC20; Fanout = 3; REG Node = '74390:3|7'
            Info: 12: + IC(2.000 ns) + CELL(7.000 ns) = 94.000 ns; Loc. = LC23; Fanout = 3; REG Node = '74390:3|3'
            Info: 13: + IC(2.000 ns) + CELL(7.000 ns) = 103.000 ns; Loc. = LC24; Fanout = 3; REG Node = '74390:3|34'
            Info: 14: + IC(2.000 ns) + CELL(6.000 ns) = 111.000 ns; Loc. = LC17; Fanout = 3; REG Node = '74390:3|31'
            Info: Total cell delay = 87.000 ns ( 78.38 % )
            Info: Total interconnect delay = 24.000 ns ( 21.62 % )
        Info: - Longest clock path from clock "clk4m" to source register is 137.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk4m'
            Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1; Fanout = 3; REG Node = '74390:1|7'
            Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC5; Fanout = 3; REG Node = '74390:1|3'
            Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC6; Fanout = 3; REG Node = '74390:1|34'
            Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC9; Fanout = 3; REG Node = '74390:1|31'
            Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC10; Fanout = 3; REG Node = '74390:2|7'
            Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 49.000 ns; Loc. = LC13; Fanout = 3; REG Node = '74390:2|3'
            Info: 8: + IC(2.000 ns) + CELL(7.000 ns) = 58.000 ns; Loc. = LC14; Fanout = 3; REG Node = '74390:2|34'
            Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 67.000 ns; Loc. = LC15; Fanout = 3; REG Node = '5'
            Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 76.000 ns; Loc. = LC19; Fanout = 3; REG Node = '74390:2|31'
            Info: 11: + IC(2.000 ns) + CELL(7.000 ns) = 85.000 ns; Loc. = LC20; Fanout = 3; REG Node = '74390:3|7'
            Info: 12: + IC(2.000 ns) + CELL(7.000 ns) = 94.000 ns; Loc. = LC23; Fanout = 3; REG Node = '74390:3|3'
            Info: 13: + IC(2.000 ns) + CELL(7.000 ns) = 103.000 ns; Loc. = LC24; Fanout = 3; REG Node = '74390:3|34'
            Info: 14: + IC(2.000 ns) + CELL(7.000 ns) = 112.000 ns; Loc. = LC17; Fanout = 3; REG Node = '74390:3|31'
            Info: 15: + IC(2.000 ns) + CELL(8.000 ns) = 122.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '74390:3|29~7'
            Info: 16: + IC(0.000 ns) + CELL(7.000 ns) = 129.000 ns; Loc. = LC25; Fanout = 3; REG Node = '74390:3|33'
            Info: 17: + IC(2.000 ns) + CELL(6.000 ns) = 137.000 ns; Loc. = LC26; Fanout = 2; REG Node = '74390:3|32'
            Info: Total cell delay = 109.000 ns ( 79.56 % )
            Info: Total interconnect delay = 28.000 ns ( 20.44 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Warning: Circuit may not operate. Detected 12 non-operational path(s) clocked by clock "clk4m" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "74390:3|32" and destination pin or register "74390:3|32" for clock "clk4m" (Hold time is 4.0 ns)
    Info: + Largest clock skew is 9.000 ns
        Info: + Longest clock path from clock "clk4m" to destination register is 137.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk4m'
            Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1; Fanout = 3; REG Node = '74390:1|7'
            Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC5; Fanout = 3; REG Node = '74390:1|3'
            Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC6; Fanout = 3; REG Node = '74390:1|34'
            Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC9; Fanout = 3; REG Node = '74390:1|31'
            Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC10; Fanout = 3; REG Node = '74390:2|7'
            Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 49.000 ns; Loc. = LC13; Fanout = 3; REG Node = '74390:2|3'
            Info: 8: + IC(2.000 ns) + CELL(7.000 ns) = 58.000 ns; Loc. = LC14; Fanout = 3; REG Node = '74390:2|34'
            Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 67.000 ns; Loc. = LC15; Fanout = 3; REG Node = '5'
            Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 76.000 ns; Loc. = LC19; Fanout = 3; REG Node = '74390:2|31'
            Info: 11: + IC(2.000 ns) + CELL(7.000 ns) = 85.000 ns; Loc. = LC20; Fanout = 3; REG Node = '74390:3|7'
            Info: 12: + IC(2.000 ns) + CELL(7.000 ns) = 94.000 ns; Loc. = LC23; Fanout = 3; REG Node = '74390:3|3'
            Info: 13: + IC(2.000 ns) + CELL(7.000 ns) = 103.000 ns; Loc. = LC24; Fanout = 3; REG Node = '74390:3|34'
            Info: 14: + IC(2.000 ns) + CELL(7.000 ns) = 112.000 ns; Loc. = LC17; Fanout = 3; REG Node = '74390:3|31'
            Info: 15: + IC(2.000 ns) + CELL(8.000 ns) = 122.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '74390:3|29~7'
            Info: 16: + IC(0.000 ns) + CELL(7.000 ns) = 129.000 ns; Loc. = LC25; Fanout = 3; REG Node = '74390:3|33'
            Info: 17: + IC(2.000 ns) + CELL(6.000 ns) = 137.000 ns; Loc. = LC26; Fanout = 2; REG Node = '74390:3|32'
            Info: Total cell delay = 109.000 ns ( 79.56 % )
            Info: Total interconnect delay = 28.000 ns ( 20.44 % )
        Info: - Shortest clock path from clock "clk4m" to source register is 128.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk4m'
            Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1; Fanout = 3; REG Node = '74390:1|7'
            Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC5; Fanout = 3; REG Node = '74390:1|3'
            Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC6; Fanout = 3; REG Node = '74390:1|34'
            Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC9; Fanout = 3; REG Node = '74390:1|31'
            Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC10; Fanout = 3; REG Node = '74390:2|7'
            Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 49.000 ns; Loc. = LC13; Fanout = 3; REG Node = '74390:2|3'
            Info: 8: + IC(2.000 ns) + CELL(7.000 ns) = 58.000 ns; Loc. = LC14; Fanout = 3; REG Node = '74390:2|34'
            Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 67.000 ns; Loc. = LC15; Fanout = 3; REG Node = '5'
            Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 76.000 ns; Loc. = LC19; Fanout = 3; REG Node = '74390:2|31'
            Info: 11: + IC(2.000 ns) + CELL(7.000 ns) = 85.000 ns; Loc. = LC20; Fanout = 3; REG Node = '74390:3|7'
            Info: 12: + IC(2.000 ns) + CELL(7.000 ns) = 94.000 ns; Loc. = LC23; Fanout = 3; REG Node = '74390:3|3'
            Info: 13: + IC(2.000 ns) + CELL(7.000 ns) = 103.000 ns; Loc. = LC24; Fanout = 3; REG Node = '74390:3|34'
            Info: 14: + IC(2.000 ns) + CELL(8.000 ns) = 113.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '74390:3|29~7'
            Info: 15: + IC(0.000 ns) + CELL(7.000 ns) = 120.000 ns; Loc. = LC25; Fanout = 3; REG Node = '74390:3|33'
            Info: 16: + IC(2.000 ns) + CELL(6.000 ns) = 128.000 ns; Loc. = LC26; Fanout = 2; REG Node = '74390:3|32'
            Info: Total cell delay = 102.000 ns ( 79.69 % )
            Info: Total interconnect delay = 26.000 ns ( 20.31 % )
    Info: - Micro clock to output delay of source is 1.000 ns
    Info: - Shortest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC26; Fanout = 2; REG Node = '74390:3|32'
        Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC26; Fanout = 2; REG Node = '74390:3|32'
        Info: Total cell delay = 8.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
Info: tco from clock "clk4m" to destination pin "clk1" through register "74390:3|31" is 116.000 ns
    Info: + Longest clock path from clock "clk4m" to source register is 111.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk4m'
        Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1; Fanout = 3; REG Node = '74390:1|7'
        Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC5; Fanout = 3; REG Node = '74390:1|3'
        Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC6; Fanout = 3; REG Node = '74390:1|34'
        Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC9; Fanout = 3; REG Node = '74390:1|31'
        Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC10; Fanout = 3; REG Node = '74390:2|7'
        Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 49.000 ns; Loc. = LC13; Fanout = 3; REG Node = '74390:2|3'
        Info: 8: + IC(2.000 ns) + CELL(7.000 ns) = 58.000 ns; Loc. = LC14; Fanout = 3; REG Node = '74390:2|34'
        Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 67.000 ns; Loc. = LC15; Fanout = 3; REG Node = '5'
        Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 76.000 ns; Loc. = LC19; Fanout = 3; REG Node = '74390:2|31'
        Info: 11: + IC(2.000 ns) + CELL(7.000 ns) = 85.000 ns; Loc. = LC20; Fanout = 3; REG Node = '74390:3|7'
        Info: 12: + IC(2.000 ns) + CELL(7.000 ns) = 94.000 ns; Loc. = LC23; Fanout = 3; REG Node = '74390:3|3'
        Info: 13: + IC(2.000 ns) + CELL(7.000 ns) = 103.000 ns; Loc. = LC24; Fanout = 3; REG Node = '74390:3|34'
        Info: 14: + IC(2.000 ns) + CELL(6.000 ns) = 111.000 ns; Loc. = LC17; Fanout = 3; REG Node = '74390:3|31'
        Info: Total cell delay = 87.000 ns ( 78.38 % )
        Info: Total interconnect delay = 24.000 ns ( 21.62 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 3; REG Node = '74390:3|31'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'clk1'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Processing ended: Mon Aug 06 10:15:39 2007
    Info: Elapsed time: 00:00:03