frequency.tan.rpt

CPLD控制交通灯程序

; N/A   ; 45.45 MHz ( period = 22.000 ns ) ; 74390:2|6  ; 74390:2|6  ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 45.45 MHz ( period = 22.000 ns ) ; 74390:1|32 ; 74390:1|32 ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 45.45 MHz ( period = 22.000 ns ) ; 74390:1|33 ; 74390:1|33 ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 45.45 MHz ( period = 22.000 ns ) ; 74390:1|5  ; 74390:1|5  ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 45.45 MHz ( period = 22.000 ns ) ; 74390:1|6  ; 74390:1|6  ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:3|31 ; 74390:3|31 ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:3|34 ; 74390:3|34 ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:3|3  ; 74390:3|3  ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:3|7  ; 74390:3|7  ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:2|31 ; 74390:2|31 ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 4          ; 5          ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 5          ; 5          ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 4          ; 4          ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:2|34 ; 74390:2|34 ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:2|3  ; 74390:2|3  ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:2|7  ; 74390:2|7  ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:1|31 ; 74390:1|31 ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:1|34 ; 74390:1|34 ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:1|3  ; 74390:1|3  ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
; N/A   ; 76.92 MHz ( period = 13.000 ns ) ; 74390:1|7  ; 74390:1|7  ; clk4m      ; clk4m    ; None                        ; None                      ; 8.000 ns                ;
+-------+----------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk4m'                                                                                                                                                             ;
+------------------------------------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From       ; To         ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; 74390:3|32 ; 74390:3|32 ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:3|33 ; 74390:3|33 ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:3|5  ; 74390:3|5  ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:3|6  ; 74390:3|6  ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:2|32 ; 74390:2|32 ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:2|33 ; 74390:2|33 ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:2|5  ; 74390:2|5  ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:2|6  ; 74390:2|6  ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:1|32 ; 74390:1|32 ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:1|33 ; 74390:1|33 ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:1|5  ; 74390:1|5  ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74390:1|6  ; 74390:1|6  ; clk4m      ; clk4m    ; None                       ; None                       ; 8.000 ns                 ;
+------------------------------------------+------------+------------+------------+----------+----------------------------+----------------------------+--------------------------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To    ; From Clock ;
+-------+--------------+------------+------------+-------+------------+
; N/A   ; None         ; 116.000 ns ; 74390:3|31 ; clk1  ; clk4m      ;
; N/A   ; None         ; 71.000 ns  ; 4          ; clk1k ; clk4m      ;
+-------+--------------+------------+------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Mon Aug 06 10:15:37 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off frequency -c frequency
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk4m" is an undefined clock
Warning: Found 25 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "74390:3|31" as buffer
    Info: Detected gated clock "74390:3|29~7" as buffer
    Info: Detected ripple clock "74390:3|33" as buffer
    Info: Detected ripple clock "74390:3|34" as buffer
    Info: Detected ripple clock "74390:3|3" as buffer
    Info: Detected gated clock "74390:3|20~7" as buffer
    Info: Detected ripple clock "74390:3|6" as buffer
    Info: Detected ripple clock "74390:3|7" as buffer
    Info: Detected ripple clock "74390:2|31" as buffer
    Info: Detected gated clock "74390:2|29~7" as buffer
    Info: Detected ripple clock "74390:2|33" as buffer
    Info: Detected ripple clock "5" as buffer
    Info: Detected ripple clock "74390:2|34" as buffer
    Info: Detected ripple clock "74390:2|3" as buffer
    Info: Detected gated clock "74390:2|20~7" as buffer
    Info: Detected ripple clock "74390:2|6" as buffer
    Info: Detected ripple clock "74390:2|7" as buffer
    Info: Detected ripple clock "74390:1|31" as buffer
    Info: Detected gated clock "74390:1|29~7" as buffer
    Info: Detected ripple clock "74390:1|33" as buffer
    Info: Detected ripple clock "74390:1|34" as buffer
    Info: Detected ripple clock "74390:1|3" as buffer
    Info: Detected gated clock "74390:1|20~7" as buffer
    Info: Detected ripple clock "74390:1|6" as buffer
    Info: Detected ripple clock "74390:1|7" as buffer
Info: Clock "clk4m" has Internal fmax of 25.64 MHz between source register "74390:3|32" and destination register "74390:3|31" (period= 39.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC26; Fanout = 2; REG Node = '74390:3|32'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC17; Fanout = 3; REG Node = '74390:3|31'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is -26.000 ns
        Info: + Shortest clock path from clock "clk4m" to destination register is 111.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk4m'
            Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1; Fanout = 3; REG Node = '74390:1|7'
            Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC5; Fanout = 3; REG Node = '74390:1|3'
            Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 22.000 ns; Loc. = LC6; Fanout = 3; REG Node = '74390:1|34'
            Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 31.000 ns; Loc. = LC9; Fanout = 3; REG Node = '74390:1|31'
            Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 40.000 ns; Loc. = LC10; Fanout = 3; REG Node = '74390:2|7'
            Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 49.000 ns; Loc. = LC13; Fanout = 3; REG Node = '74390:2|3'
            Info: 8: + IC(2.000 ns) + CELL(7.000 ns) = 58.000 ns; Loc. = LC14; Fanout = 3; REG Node = '74390:2|34'