📄 controller.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY controller IS
PORT
(
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
hold : IN STD_LOGIC;
flash : OUT STD_LOGIC;
numa,numb : OUT INTEGER RANGE 0 TO 25;
reda,greena,yellowa: OUT STD_LOGIC;
redb,greenb,yellowb: OUT STD_LOGIC
);
END controller;
ARCHITECTURE a OF controller IS
SIGNAL countnum : INTEGER RANGE 0 TO 50;
BEGIN
PROCESS (clock)
BEGIN
IF reset = '0' THEN
countnum <= 0;
ELSIF rising_edge(clock) THEN
IF hold = '0' THEN
flash <= '1';
ELSE
flash <= '0';
IF countnum = 49 THEN
countnum <= 0;
ELSE
countnum <= countnum+1;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (clock)
BEGIN
IF rising_edge(clock) THEN
IF hold = '0' THEN
reda <= '1';
redb <= '1';
greena <= '0';
greenb <= '0';
yellowa <= '0';
yellowb <= '0';
ELSE
IF countnum <= 19 THEN
numa <= 20-countnum;
reda <= '0';
greena <= '1';
yellowa <= '0';
ELSIF countnum <=24 THEN
numa <= 25-countnum;
reda <= '0';
greena <= '0';
yellowa <= '1';
ELSE
numa <= 50-countnum;
reda <= '1';
greena <= '0';
yellowa <= '0';
END IF;
IF countnum <=24 THEN
numb <= 25-countnum;
redb <= '1';
greenb <= '0';
yellowb <= '0';
ELSIF countnum <=44 THEN
numb <= 45-countnum;
redb <= '0';
greenb <= '1';
yellowb <= '0';
ELSE
numb <= 50-countnum;
redb <= '0';
greenb <= '0';
yellowb <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END a;
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