fenei.tan.rpt

CPLD控制交通灯程序

; N/A   ; None         ; 11.000 ns  ; numin[2] ; numb[1]~reg0 ; clock    ;
; N/A   ; None         ; 11.000 ns  ; numin[2] ; numb[3]~reg0 ; clock    ;
; N/A   ; None         ; 11.000 ns  ; numin[0] ; numb[0]~reg0 ; clock    ;
; N/A   ; None         ; 11.000 ns  ; numin[0] ; numa[0]~reg0 ; clock    ;
; N/A   ; None         ; 11.000 ns  ; numin[0] ; numb[1]~reg0 ; clock    ;
; N/A   ; None         ; 11.000 ns  ; numin[0] ; numb[3]~reg0 ; clock    ;
+-------+--------------+------------+----------+--------------+----------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 8.000 ns   ; numb[3]~reg0 ; numb[3] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numb[1]~reg0 ; numb[1] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numa[0]~reg0 ; numa[0] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numb[2]~reg0 ; numb[2] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numa[1]~reg0 ; numa[1] ; clock      ;
; N/A   ; None         ; 8.000 ns   ; numb[0]~reg0 ; numb[0] ; clock      ;
+-------+--------------+------------+--------------+---------+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+----------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From     ; To           ; To Clock ;
+---------------+-------------+-----------+----------+--------------+----------+
; N/A           ; None        ; -3.000 ns ; numin[1] ; numb[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[1] ; numa[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[1] ; numb[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[1] ; numb[3]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[4] ; numa[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[4] ; numb[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[4] ; numa[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[4] ; numb[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[4] ; numb[3]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[3] ; numa[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[3] ; numb[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[3] ; numa[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[3] ; numb[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[3] ; numb[3]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[2] ; numa[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[2] ; numb[2]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[2] ; numa[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[2] ; numb[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[2] ; numb[3]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[0] ; numb[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[0] ; numa[0]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[0] ; numb[1]~reg0 ; clock    ;
; N/A           ; None        ; -3.000 ns ; numin[0] ; numb[3]~reg0 ; clock    ;
+---------------+-------------+-----------+----------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
    Info: Processing started: Sun Aug 05 22:48:34 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fenei -c fenei
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clock"
Info: tsu for register "numb[2]~reg0" (data pin = "numin[1]", clock pin = "clock") is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 7; PIN Node = 'numin[1]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'numb[2]~reg0'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock "clock" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'numb[2]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock "clock" to destination pin "numb[3]" through register "numb[3]~reg0" is 8.000 ns
    Info: + Longest clock path from clock "clock" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC14; Fanout = 1; REG Node = 'numb[3]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC14; Fanout = 1; REG Node = 'numb[3]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_5; Fanout = 0; PIN Node = 'numb[3]'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: th for register "numb[2]~reg0" (data pin = "numin[1]", clock pin = "clock") is -3.000 ns
    Info: + Longest clock path from clock "clock" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'numb[2]~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_81; Fanout = 7; PIN Node = 'numin[1]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC8; Fanout = 1; REG Node = 'numb[2]~reg0'
        Info: Total cell delay = 8.000 ns ( 80.00 % )
        Info: Total interconnect delay = 2.000 ns ( 20.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun Aug 05 22:48:34 2007
    Info: Elapsed time: 00:00:01