display.map.eqn

CPLD控制交通灯程序

-- Copyright (C) 1991-2006 Altera Corporation
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--A1L12Q is display[4]~reg0
A1L12Q_p1_out = qin[3] & qin[1];
A1L12Q_p2_out = !qin[1] & qin[2];
A1L12Q_or_out = A1L12Q_p1_out # A1L12Q_p2_out # qin[0];
A1L12Q_reg_input = A1L12Q_or_out;
A1L12Q = DFFE(A1L12Q_reg_input, GLOBAL(clock), , , );


--A1L14Q is display[5]~reg0
A1L14Q_p1_out = qin[3] & qin[2];
A1L14Q_p2_out = !qin[3] & !qin[2] & qin[0];
A1L14Q_p3_out = qin[0] & qin[1];
A1L14Q_p4_out = !qin[2] & qin[1];
A1L14Q_or_out = A1L14Q_p1_out # A1L14Q_p2_out # A1L14Q_p3_out # A1L14Q_p4_out;
A1L14Q_reg_input = A1L14Q_or_out;
A1L14Q = DFFE(A1L14Q_reg_input, GLOBAL(clock), , , );


--A1L8Q is display[2]~reg0
A1L8Q_p1_out = !qin[0] & qin[1] & !qin[2];
A1L8Q_p2_out = qin[1] & qin[3];
A1L8Q_p3_out = qin[2] & qin[3];
A1L8Q_or_out = A1L8Q_p1_out # A1L8Q_p2_out # A1L8Q_p3_out;
A1L8Q_reg_input = A1L8Q_or_out;
A1L8Q = DFFE(A1L8Q_reg_input, GLOBAL(clock), , , );


--A1L16Q is display[6]~reg0
A1L16Q_p1_out = !qin[0] & qin[2] & !qin[3];
A1L16Q_p2_out = qin[2] & !qin[3] & !qin[1];
A1L16Q_p3_out = !qin[2] & !qin[3] & qin[1];
A1L16Q_p4_out = !qin[2] & qin[3] & !qin[1];
A1L16Q_or_out = A1L16Q_p1_out # A1L16Q_p2_out # A1L16Q_p3_out # A1L16Q_p4_out;
A1L16Q_reg_input = !(A1L16Q_or_out);
A1L16Q = DFFE(A1L16Q_reg_input, GLOBAL(clock), , , );


--A1L6Q is display[1]~reg0
A1L6Q_p1_out = qin[3] & qin[1];
A1L6Q_p2_out = !qin[1] & qin[2] & qin[0];
A1L6Q_p3_out = qin[3] & qin[2];
A1L6Q_p4_out = qin[1] & qin[2] & !qin[0];
A1L6Q_or_out = A1L6Q_p1_out # A1L6Q_p2_out # A1L6Q_p3_out # A1L6Q_p4_out;
A1L6Q_reg_input = A1L6Q_or_out;
A1L6Q = DFFE(A1L6Q_reg_input, GLOBAL(clock), , , );


--A1L4Q is display[0]~reg0
A1L4Q_p1_out = !qin[0] & !qin[1] & !qin[2];
A1L4Q_p2_out = qin[1] & !qin[3];
A1L4Q_p3_out = qin[0] & qin[2] & !qin[3];
A1L4Q_p4_out = !qin[1] & !qin[2] & qin[3];
A1L4Q_or_out = A1L4Q_p1_out # A1L4Q_p2_out # A1L4Q_p3_out # A1L4Q_p4_out;
A1L4Q_reg_input = !(A1L4Q_or_out);
A1L4Q = DFFE(A1L4Q_reg_input, GLOBAL(clock), , , );


--A1L10Q is display[3]~reg0
A1L10Q_p0_out = qin[2] & qin[0] & qin[1];
A1L10Q_p1_out = !qin[2] & !qin[3] & qin[0] & !qin[1];
A1L10Q_p2_out = qin[2] & !qin[0] & !qin[1];
A1L10Q_p3_out = qin[2] & qin[3];
A1L10Q_p4_out = qin[3] & qin[1];
A1L10Q_or_out = A1L10Q_p0_out # A1L10Q_p1_out # A1L10Q_p2_out # A1L10Q_p3_out # A1L10Q_p4_out;
A1L10Q_reg_input = A1L10Q_or_out;
A1L10Q = DFFE(A1L10Q_reg_input, GLOBAL(clock), , , );


--clock is clock
--operation mode is input

clock = INPUT();


--qin[0] is qin[0]
--operation mode is input

qin[0] = INPUT();


--qin[1] is qin[1]
--operation mode is input

qin[1] = INPUT();


--qin[2] is qin[2]
--operation mode is input

qin[2] = INPUT();


--qin[3] is qin[3]
--operation mode is input

qin[3] = INPUT();


--display[4] is display[4]
--operation mode is output

display[4] = OUTPUT(A1L12Q);


--display[2] is display[2]
--operation mode is output

display[2] = OUTPUT(A1L8Q);


--display[5] is display[5]
--operation mode is output

display[5] = OUTPUT(A1L14Q);


--display[6] is display[6]
--operation mode is output

display[6] = OUTPUT(A1L16Q);


--display[0] is display[0]
--operation mode is output

display[0] = OUTPUT(A1L4Q);


--display[1] is display[1]
--operation mode is output

display[1] = OUTPUT(A1L6Q);


--display[3] is display[3]
--operation mode is output

display[3] = OUTPUT(A1L10Q);